Re: [PATCH] pci: fix nit in ROM BAR size probing

[Jesse Barnes]

On Wed, 4 Nov 2009 19:06:19 +0200
"Michael S. Tsirkin" <mst@xxxxxxxxxx> wrote:

> On Wed, Nov 04, 2009 at 09:04:09AM -0800, Jesse Barnes wrote:
> > On Thu, 29 Oct 2009 17:24:59 +0200
> > "Michael S. Tsirkin" <mst@xxxxxxxxxx> wrote:
> > 
> > > When probing for ROM BAR size, we should not
> > > change bits 1:10 in this BAR, because these
> > > bits are marked as "reserved for future use" in PCI spec,
> > > so changing them might have side effects.
> > > 
> > > No such issue for I/O or memory, as there is
> > > an implementation note in PCI spec which explicitly allows
> > > writing 0xfffffffff there.
> > > 
> > > Signed-off-by: Michael S. Tsirkin <mst@xxxxxxxxxx>
> > > ---
> > >  drivers/pci/probe.c |    4 ++--
> > >  1 files changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> > > index 8105e32..d65aae4 100644
> > > --- a/drivers/pci/probe.c
> > > +++ b/drivers/pci/probe.c
> > > @@ -163,12 +163,12 @@ int __pci_read_base(struct pci_dev *dev,
> > > enum pci_bar_type type, {
> > >  	u32 l, sz, mask;
> > >  
> > > -	mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
> > > +	mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
> > >  
> > >  	res->name = pci_name(dev);
> > >  
> > >  	pci_read_config_dword(dev, pos, &l);
> > > -	pci_write_config_dword(dev, pos, mask);
> > > +	pci_write_config_dword(dev, pos, l | mask);
> > >  	pci_read_config_dword(dev, pos, &sz);
> > >  	pci_write_config_dword(dev, pos, l);
> > 
> > Applied to linux-next, thanks.  Another possible enhancement here
> > would be to make the mask into a switch based on the type, since
> > mem32 and mem64 "BARs" (added by willy for doing BAR-like stuff)
> > could probably use ~0 as well.
> > 
> > Jesse
> 
> Where can I find the patch by willy that adds these?

commit 6ac665c63dcac8fcec534a1d224ecbb8b867ad59
Author: Matthew Wilcox <matthew@xxxxxx>
Date:   Mon Jul 28 13:38:59 2008 -0400

    PCI: rewrite PCI BAR reading code



-- 
Jesse Barnes, Intel Open Source Technology Center
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