Re: [PATCH 3/5] perf, x86: Disable PEBS on clowertown chips

[Stephane Eranian]

On Fri, Mar 5, 2010 at 2:25 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> On Fri, 2010-03-05 at 13:57 -0800, Stephane Eranian wrote:
>
>> When I read AJ68, my understanding is that it's not that you do not
>> get the interrupt. It will be delayed by one event. The buffer will become
>> full. You won't overrun the buffer, you will get the interrupt at the next
>> event. On interrupt, you have to reset the PEBS position pointer anyway.
>> There is already a disconnect between the sampling period and the actual
>> instruction sampled. That's not making the situation that much worse, unless
>> I am missing something.
>
> The current code doesn't use the buffering at all, it uses single-shot
> PEBS by keeping pebs_event_reset 0 and setting a threshold of a single
> entry, so if due to AJ68 we miss a PMI it will never come.
>
What stops PEBS is that it crosses the end of the buffer. The buffer
is one-deep,
threshold = buffer end, you get a single sample. reset has nothing to
do with this.

AJ68 does not say you miss a PMI, it says the PMI comes at the next
event. I suspect they mean the next observed event, and not necessarily
the next recorded event. But I can check on that.


> I guess we can fudge something, but at what point does the whole thing
> stop being useful?

What matters is that you get a valid sample.

>
> It would end up being something with fuzzy period and fuzzy location,
> which is a loss-loss situation if you ask me.
>
The period is already fuzzy to begin with. Recall our discussion a couple
of weeks back.
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