Re: USB mass storage and ARM cache coherency
From: Benjamin Herrenschmidt
Date: Sat Mar 06 2010 - 16:09:09 EST
On Sat, 2010-03-06 at 19:36 +0000, Russell King - ARM Linux wrote:
> On Sat, Mar 06, 2010 at 04:17:23PM +0530, James Bottomley wrote:
> > On a fault in of exec data, we first try to get the page out of the page
> > cache. If it's not present, we put the faulting process to sleep and
> > fetch it in from storage. When we do the read, on the PIO path, the
> > kernel alias for the page becomes dirty. Some time later, we place the
> > page into the user space (updating the pte entry that caused a fault).
> > At this point, we'll call both flush_icache_page() and
> > update_mmu_cache() ... this is where the I/D resolution should be done.
> No - this is where things get extremely icky.
> The problem at this point occurs on SMP architectures. As soon as you
> update the PTE entry, it is visible to other threads of the application.
> If you do I-cache handling after updating the PTE, then there is a window
> where another CPU can execute the page:
Right, we actually hit that bug on powerpc, however, James explanation
is misleading, ie, I think the -code- actually is right and
flush_icache_page() is called before set_pte_at(). However, see my other
email, I have other issues with it as it is, but nothing unfixable.
So for now, I keep my flush in set_pte_at() and ptep_set_access_flags(),
we'll see if I can move that to an improved flush_icache_page(). In
fact, even set_pte_at() isn't a panacea for me, as I want the fault type
> CPU0 CPU1
> speculatively prefetches from page N via kernel
> mapping, loads garbage into I-cache
> attempts to execute P
> page fault
> page N allocated
> executes P
> flush I-cache
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