RFC [PATCH 1/4] staging: sep: header file updates for 12/09 softwa=

[Mark Allyn]

Signed-off-by: Mark A. Allyn <mark.a.allyn@xxxxxxxxx>
---
  drivers/staging/sep/sep_dev.h            |  110 -----
  drivers/staging/sep/sep_driver_api.h     |  769 ++++++++++++++++++-------=
-----
  drivers/staging/sep/sep_driver_config.h  |  140 ++++--
  drivers/staging/sep/sep_driver_ext_api.h |  127 +++++
  drivers/staging/sep/sep_driver_hw_defs.h |  426 +++++++++--------
  5 files changed, 921 insertions(+), 651 deletions(-)
  delete mode 100644 drivers/staging/sep/sep_dev.h
  create mode 100644 drivers/staging/sep/sep_driver_ext_api.h

diff --git a/drivers/staging/sep/sep_dev.h b/drivers/staging/sep/sep_dev.h
deleted file mode 100644
index 9200524..0000000
--- a/drivers/staging/sep/sep_dev.h
+++ /dev/null
@@ -1,110 +0,0 @@
-#ifndef __SEP_DEV_H__
-#define __SEP_DEV_H__
-
-/*
- *
- *  sep_dev.h - Security Processor Device Structures
- *
- *  Copyright(c) 2009 Intel Corporation. All rights reserved.
- *  Copyright(c) 2009 Discretix. All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify i=
t
- *  under the terms of the GNU General Public License as published by the =
Free
- *  Software Foundation; either version 2 of the License, or (at your opti=
on)
- *  any later version.
- *
- *  This program is distributed in the hope that it will be useful, but WI=
THOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License =
for
- *  more details.
- *
- *  You should have received a copy of the GNU General Public License alon=
g with
- *  this program; if not, write to the Free Software Foundation, Inc., 59
- *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- *
- *  CONTACTS:
- *
- *  Alan Cox           alan@xxxxxxxxxxxxxxx
- *
- */
-
-struct sep_device {
-       /* pointer to pci dev */
-       struct pci_dev *pdev;
-
-       unsigned long in_use;
-
-       /* address of the shared memory allocated during init for SEP drive=
r
-          (coherent alloc) */
-       void *shared_addr;
-       /* the physical address of the shared area */
-       dma_addr_t shared_bus;
-
-       /* restricted access region (coherent alloc) */
-       dma_addr_t rar_bus;
-       void *rar_addr;
-       /* firmware regions: cache is at rar_addr */
-       unsigned long cache_size;
-
-       /* follows the cache */
-       dma_addr_t resident_bus;
-       unsigned long resident_size;
-       void *resident_addr;
-
-       /* start address of the access to the SEP registers from driver */
-       void __iomem *reg_addr;
-       /* transaction counter that coordinates the transactions between SE=
P and HOST */
-       unsigned long send_ct;
-       /* counter for the messages from sep */
-       unsigned long reply_ct;
-       /* counter for the number of bytes allocated in the pool for the cu=
rrent
-          transaction */
-       unsigned long data_pool_bytes_allocated;
-
-       /* array of pointers to the pages that represent input data for the=
 synchronic
-          DMA action */
-       struct page **in_page_array;
-
-       /* array of pointers to the pages that represent out data for the s=
ynchronic
-          DMA action */
-       struct page **out_page_array;
-
-       /* number of pages in the sep_in_page_array */
-       unsigned long in_num_pages;
-
-       /* number of pages in the sep_out_page_array */
-       unsigned long out_num_pages;
-
-       /* global data for every flow */
-       struct sep_flow_context_t flows[SEP_DRIVER_NUM_FLOWS];
-
-       /* pointer to the workqueue that handles the flow done interrupts *=
/
-       struct workqueue_struct *flow_wq;
-
-};
-
-static struct sep_device *sep_dev;
-
-static inline void sep_write_reg(struct sep_device *dev, int reg, u32 valu=
e)
-{
-       void __iomem *addr =3D dev->reg_addr + reg;
-       writel(value, addr);
-}
-
-static inline u32 sep_read_reg(struct sep_device *dev, int reg)
-{
-       void __iomem *addr =3D dev->reg_addr + reg;
-       return readl(addr);
-}
-
-/* wait for SRAM write complete(indirect write */
-static inline void sep_wait_sram_write(struct sep_device *dev)
-{
-       u32 reg_val;
-       do
-               reg_val =3D sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
-       while (!(reg_val & 1));
-}
-
-
-#endif
diff --git a/drivers/staging/sep/sep_driver_api.h b/drivers/staging/sep/sep=
_driver_api.h
index 383543d..05ec048 100644
--- a/drivers/staging/sep/sep_driver_api.h
+++ b/drivers/staging/sep/sep_driver_api.h
@@ -1,23 +1,29 @@
-/*
- *
- *  sep_driver_api.h - Security Processor Driver api definitions
- *
- *  Copyright(c) 2009 Intel Corporation. All rights reserved.
- *  Copyright(c) 2009 Discretix. All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify i=
t
- *  under the terms of the GNU General Public License as published by the =
Free
- *  Software Foundation; either version 2 of the License, or (at your opti=
on)
- *  any later version.
+ /*
+ *   sep_driver_api.h
   *
- *  This program is distributed in the hope that it will be useful, but WI=
THOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License =
for
- *  more details.
- *
- *  You should have received a copy of the GNU General Public License alon=
g with
- *  this program; if not, write to the Free Software Foundation, Inc., 59
- *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *************************************************************************=
*
+ *   Copyright 2009 (c) Discretix Technologies Ltd.                       =
   *
+ *   Copyright 2009 (c) Intel Corporation                                 =
   *
+ *                                                                        =
 *
+ *   This software is protected by copyright, international treaties and  =
 *
+ *   various patents. Any copy or reproduction of this Software as        =
 *
+ *   permitted below, must include this Copyright Notice as well as any   =
 *
+ *   other notices provided under such license.                           =
 *
+ *                                                                        =
 *
+ *   This program shall be governed by, and may be used and redistributed =
 *
+ *   under the terms and conditions of the GNU General Public License,    =
 *
+ *   version 2, as published by the Free Software Foundation.             =
 *
+ *                                                                        =
 *
+ *   This program is distributed in the hope that it will be useful,      =
 *
+ *   but WITHOUT ANY liability and WARRANTY; without even the implied     =
 *
+ *   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     =
 *
+ *   See the GNU General Public License for more details.                 =
 *
+ *                                                                        =
 *
+ *   You should have received a copy of the GNU General Public License    =
 *
+ *   along with this program; if not, please write to the Free Software   =
 *
+ *   Foundation, Inc.,                                                    =
 *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.            =
 *
+ *************************************************************************=
*
   *
   *  CONTACTS:
   *
@@ -25,401 +31,576 @@
   *
   *  CHANGES:
   *
- *  2009.06.26 Initial publish
+ *  2010.01.08 Initial publish
   *
   */
-
  #ifndef __SEP_DRIVER_API_H__
  #define __SEP_DRIVER_API_H__

+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/kdev_t.h>
+#include <linux/mutex.h>
+#include <linux/mm.h>
+#include <linux/poll.h>
+#include <linux/wait.h>

+/*-----------------
+    DEFINE
+-------------------*/

-/*----------------------------------------------------------------
-  IOCTL command defines
-  -----------------------------------------------------------------*/
+#define SEP_DRIVER_SRC_REPLY    1
+#define SEP_DRIVER_SRC_REQ      2
+#define SEP_DRIVER_SRC_PRINTF   3

-/* magic number 1 of the sep IOCTL command */
-#define SEP_IOC_MAGIC_NUMBER                           's'

-/* sends interrupt to sep that message is ready */
-#define SEP_IOCSENDSEPCOMMAND                 _IO(SEP_IOC_MAGIC_NUMBER , 0=
)

-/* sends interrupt to sep that message is ready */
-#define SEP_IOCSENDSEPRPLYCOMMAND             _IO(SEP_IOC_MAGIC_NUMBER , 1=
)
+/*-------------------------------------------
+    TYPEDEFS
+----------------------------------------------*/

-/* allocate memory in data pool */
-#define SEP_IOCALLOCDATAPOLL                  _IO(SEP_IOC_MAGIC_NUMBER , 2=
)
+/*
+  init command struct
+*/
+struct sep_driver_init_t {
+  /* start of the 1G of the host memory address that SEP can access */
+  u32 *message_addr;

-/* write to pre-allocated  memory in data pool */
-#define SEP_IOCWRITEDATAPOLL                  _IO(SEP_IOC_MAGIC_NUMBER , 3=
)
+  /* start address of resident */
+  u32   message_size_in_words;

-/* read from  pre-allocated  memory in data pool */
-#define SEP_IOCREADDATAPOLL                   _IO(SEP_IOC_MAGIC_NUMBER , 4=
)
+  /* offset of the init message in the sep sram */
+  u32   sep_sram_addr;
+};

-/* create sym dma lli tables */
-#define SEP_IOCCREATESYMDMATABLE              _IO(SEP_IOC_MAGIC_NUMBER , 5=
)

-/* create flow dma lli tables */
-#define SEP_IOCCREATEFLOWDMATABLE             _IO(SEP_IOC_MAGIC_NUMBER , 6=
)
+/*
+  realloc cache resident command
+*/
+struct sep_driver_realloc_cache_resident_t {
+  /* base address */
+  void  *base_addr;

-/* free dynamic data aalocated during table creation */
-#define SEP_IOCFREEDMATABLEDATA                _IO(SEP_IOC_MAGIC_NUMBER , =
7)
+  /* current cache address */
+  void  *cache_addr;

-/* get the static pool area addersses (physical and virtual) */
-#define SEP_IOCGETSTATICPOOLADDR               _IO(SEP_IOC_MAGIC_NUMBER , =
8)
+  /* cache size in bytes*/
+  u32   cache_size_in_bytes;

-/* set flow id command */
-#define SEP_IOCSETFLOWID                       _IO(SEP_IOC_MAGIC_NUMBER , =
9)
+  /* current resident address */
+  void  *resident_addr;

-/* add tables to the dynamic flow */
-#define SEP_IOCADDFLOWTABLE                    _IO(SEP_IOC_MAGIC_NUMBER , =
10)
+  /* resident size in bytes*/
+  u32   resident_size_in_bytes;

-/* add flow add tables message */
-#define SEP_IOCADDFLOWMESSAGE                  _IO(SEP_IOC_MAGIC_NUMBER , =
11)
+  /* current dcache address */
+  void  *dcache_addr;

-/* start sep command */
-#define SEP_IOCSEPSTART                        _IO(SEP_IOC_MAGIC_NUMBER , =
12)
+  /* resident size in bytes*/
+  u32   dcache_size_in_bytes;

-/* init sep command */
-#define SEP_IOCSEPINIT                         _IO(SEP_IOC_MAGIC_NUMBER , =
13)
+  /* ext cache current address */
+  void  *extcache_addr;

-/* end transaction command */
-#define SEP_IOCENDTRANSACTION                  _IO(SEP_IOC_MAGIC_NUMBER , =
15)
+  /* ext cache size in bytes*/
+  u32   extcache_size_in_bytes;

-/* reallocate cache and resident */
-#define SEP_IOCREALLOCCACHERES                 _IO(SEP_IOC_MAGIC_NUMBER , =
16)
+  /* new cache address */
+  dma_addr_t   new_cache_addr;

-/* get the offset of the address starting from the beginnnig of the map ar=
ea */
-#define SEP_IOCGETMAPPEDADDROFFSET             _IO(SEP_IOC_MAGIC_NUMBER , =
17)
+  /* new resident address */
+  dma_addr_t   new_resident_addr;

-/* get time address and value */
-#define SEP_IOCGETIME                          _IO(SEP_IOC_MAGIC_NUMBER , =
19)
+  /* new dcache address */
+  dma_addr_t   new_dcache_addr;

-/*-------------------------------------------
-    TYPEDEFS
-----------------------------------------------*/
+  /* new resident address */
+  dma_addr_t   new_shared_area_addr;

-/*
-  init command struct
-*/
-struct sep_driver_init_t {
-       /* start of the 1G of the host memory address that SEP can access *=
/
-       unsigned long message_addr;
+  /* new base address */
+  dma_addr_t   new_base_addr;
+};
+
+
+struct sep_driver_realloc_ext_cache_t {
+  /* current external cache address */
+  void  *ext_cache_addr;
+
+  /* external cache size in bytes*/
+  u32   ext_cache_size_in_bytes;

-       /* start address of resident */
-       unsigned long message_size_in_words;
+  /* new external cache address */
+  dma_addr_t   new_ext_cache_addr;

  };

+struct sep_driver_alloc_t {
+  /* virtual address of allocated space */
+  u32 offset;
+
+  /* physical address of allocated space */
+  dma_addr_t bus_address;
+
+  /* number of bytes to allocate */
+  u32 num_bytes;
+};

  /*
-  realloc cache resident command
  */
-struct sep_driver_realloc_cache_resident_t {
-       /* new cache address */
-       u64 new_cache_addr;
-       /* new resident address */
-       u64 new_resident_addr;
-       /* new resident address */
-       u64  new_shared_area_addr;
-       /* new base address */
-       u64 new_base_addr;
+struct sep_driver_build_sync_table_t {
+  /* address value of the data in */
+  unsigned long  app_in_address;
+
+  /* size of data in */
+  u32  data_in_size;
+
+  /* address of the data out */
+  unsigned long  app_out_address;
+
+  /* the size of the block of the operation - if needed,
+  every table will be modulo this parameter */
+  u32  block_size;
+
+  /* the physical address of the first input DMA table */
+  dma_addr_t  in_table_address;
+
+  /* number of entries in the first input DMA table */
+  u32  in_table_num_entries;
+
+  /* the physical address of the first output DMA table */
+  dma_addr_t  out_table_address;
+
+  /* number of entries in the first output DMA table */
+  u32  out_table_num_entries;
+
+  /* data in the first input table */
+  u32  table_data_size;
+
+  /* distinct user/kernel layout */
+  bool isKernelVirtualAddress;
+
  };

-struct sep_driver_alloc_t {
-       /* virtual address of allocated space */
-       unsigned long offset;

-       /* physical address of allocated space */
-       unsigned long phys_address;
+/* command struct for static pool addresses  */
+struct sep_driver_static_pool_addr_t {
+  /* physical address of the static pool */
+  dma_addr_t   static_bus_address;

-       /* number of bytes to allocate */
-       unsigned long num_bytes;
+  /* virtual address of the static pool */
+  void   *static_virt_address;
  };

-/*
- */
-struct sep_driver_write_t {
-       /* application space address */
-       unsigned long app_address;
+/* command struct for getiing offset of the physical address from
+       the start of the mapped area  */
+struct sep_driver_get_mapped_offset_t {
+  /* physical address of the static pool */
+  dma_addr_t   bus_address;

-       /* address of the data pool */
-       unsigned long datapool_address;
+  /* virtual address of the static pool */
+  u32   offset;
+};

-       /* number of bytes to write */
-       unsigned long num_bytes;
+/* command struct for getting time value and address */
+struct sep_driver_get_time_t {
+  /* physical address of stored time */
+  dma_addr_t   time_bus_address;
+
+  /* value of the stored time */
+  u32   time_value;
  };

-/*
- */
-struct sep_driver_read_t {
-       /* application space address */
-       unsigned long app_address;
+/* command struct for getting time value and address */
+struct sep_driver_set_caller_id_t {
+  /* pid of the process */
+  u32   pid;
+
+  /* virtual address of the caller id hash */
+  void  *callerIdAddress;

-       /* address of the data pool */
-       unsigned long datapool_address;
+  /* caller id hash size in bytes */
+  u32   callerIdSizeInBytes;

-       /* number of bytes to read */
-       unsigned long num_bytes;
  };

+/* command struct for translating rar handle to bus address
+   and setting it at predefined location */
+struct sep_driver_rar_handle_to_bus {
+
+       /* rar handle */
+       void  *rar_handle;
+};
+
+
  /*
+  structure that represent one entry in the DMA LLI table
  */
-struct sep_driver_build_sync_table_t {
-       /* address value of the data in */
-       unsigned long app_in_address;
+struct sep_lli_entry_t {
+  /* physical address */
+  u32  bus_address;
+
+  /* block size */
+  u32  block_size;
+};

-       /* size of data in */
-       unsigned long data_in_size;

-       /* address of the data out */
-       unsigned long app_out_address;

-       /* the size of the block of the operation - if needed,
-          every table will be modulo this parameter */
-       unsigned long block_size;
+struct sep_caller_id_entry {

-       /* the physical address of the first input DMA table */
-       unsigned long in_table_address;
+  int pid;

-       /* number of entries in the first input DMA table */
-       unsigned long in_table_num_entries;
+  unsigned char callerIdHash[SEP_CALLER_ID_HASH_SIZE_IN_BYTES];
+
+};

-       /* the physical address of the first output DMA table */
-       unsigned long out_table_address;

-       /* number of entries in the first output DMA table */
-       unsigned long out_table_num_entries;

-       /* data in the first input table */
-       unsigned long table_data_size;
+/**
+ * @struct sep_dma_map
+ *
+ * Structure that contains all information needed for mapping the user pag=
es
+ *           or kernel buffers for dma operations
+ *
+ *
+ */
+struct sep_dma_map {

-       /* distinct user/kernel layout */
-       bool isKernelVirtualAddress;
+  /* mapped dma address */
+  dma_addr_t    dma_addr;

+  /* size of the mapped data */
+  size_t        size;
  };

+
  /*
+    context of the device
  */
-struct sep_driver_build_flow_table_t {
-       /* flow type */
-       unsigned long flow_type;
+struct device_context {

-       /* flag for input output */
-       unsigned long input_output_flag;
+    /* the following addresses are for the restricted access region */
+    void *rar_virtual_address;

-       /* address value of the data in */
-       unsigned long virt_buff_data_addr;
+    dma_addr_t rar_physical_address;

-       /* size of data in */
-       unsigned long num_virtual_buffers;
+    dma_addr_t rar_start_address;
+    dma_addr_t rar_end_address;
+    size_t rar_size;

-       /* the physical address of the first input DMA table */
-       unsigned long first_table_addr;
+    /* address of the shared memory allocated during init for SEP driver *=
/
+    void  *shared_area_virt_addr;

-       /* number of entries in the first input DMA table */
-       unsigned long first_table_num_entries;
+    /* the physical address of the shared area */
+    dma_addr_t  shared_area_bus_addr;

-       /* data in the first input table */
-       unsigned long first_table_data_size;
+    /* mapped dma address of the shared area */
+    dma_addr_t  shared_area_dma_addr;

-       /* distinct user/kernel layout */
-       bool isKernelVirtualAddress;
-};
+    /* shared area size */
+    size_t     shared_area_size;

+    /* major and minor device numbers */
+    dev_t   device_number;

-struct sep_driver_add_flow_table_t {
-       /* flow id  */
-       unsigned long flow_id;
+    int sep_irq;

-       /* flag for input output */
-       unsigned long inputOutputFlag;
+    /* cdev struct of the driver */
+    struct cdev                        cdev;

-       /* address value of the data in */
-       unsigned long virt_buff_data_addr;
+    struct pci_dev             *pdev;
+    /*
+      signals if the SeP is already used for an API,
+      updated with atomic operations
+    */
+    unsigned long   in_use_flag;

-       /* size of data in */
-       unsigned long num_virtual_buffers;
+    /* mutex for locking access to ioctl from different threads */
+    struct mutex               ioctl_mutex;

-       /* address of the first table */
-       unsigned long first_table_addr;
+    /* wait queue head (event) of the driver */
+    wait_queue_head_t          event;

-       /* number of entries in the first table */
-       unsigned long first_table_num_entries;

-       /* data size of the first table */
-       unsigned long first_table_data_size;
+    /* start address of the access to the SEP registers from driver */
+    void __iomem *reg_addr;

-       /* distinct user/kernel layout */
-       bool isKernelVirtualAddress;
+    /* device pointer, used for DMA APIs - initialized either as
+       platform device (default), or according to the type of the SeP
+       on the platform (PCI etc' ) */
+    struct device *dev_ptr;

-};
+    /* transaction counter that coordinates the transactions
+    between SEP and HOST */
+    u32                        host_to_sep_send_counter;

-/*
-  command struct for set flow id
-*/
-struct sep_driver_set_flow_id_t {
-       /* flow id to set */
-       unsigned long flow_id;
-};
+    /* counter for the messages from sep */
+    u32                        sep_to_host_reply_counter;

+    /* counter for the number of bytes allocated in the pool for the curre=
nt
+    transaction */
+    u32                        data_pool_bytes_allocated;

-/* command struct for add tables message */
-struct sep_driver_add_message_t {
-       /* flow id to set */
-       unsigned long flow_id;
+    /* number of the lli tables created in the current transaction */
+    u32     num_lli_tables_created;

-       /* message size in bytes */
-       unsigned long message_size_in_bytes;
+    /* array of pointers to the pages that represent
+    input data for the synchronic DMA action */
+    struct page                **in_page_array;

-       /* address of the message */
-       unsigned long message_address;
-};
+    /* array of pointers to the pages that represent out
+    data for the synchronic DMA action */
+    struct page                **out_page_array;

-/* command struct for static pool addresses  */
-struct sep_driver_static_pool_addr_t {
-       /* physical address of the static pool */
-       unsigned long physical_static_address;
+    /* number of pages in the sep_in_page_array */
+    u32                                        in_num_pages;

-       /* virtual address of the static pool */
-       unsigned long virtual_static_address;
-};
+    /* number of pages in the sep_out_page_array */
+    u32                                        out_num_pages;

-/* command struct for getiing offset of the physical address from
-       the start of the mapped area  */
-struct sep_driver_get_mapped_offset_t {
-       /* physical address of the static pool */
-       unsigned long physical_address;
+    /* map array of the input data */
+    struct sep_dma_map  *in_map_array;

-       /* virtual address of the static pool */
-       unsigned long offset;
-};
+    /* map array of the output data */
+    struct sep_dma_map  *out_map_array;

-/* command struct for getting time value and address */
-struct sep_driver_get_time_t {
-       /* physical address of stored time */
-       unsigned long time_physical_address;
+    /* number of entries of the input mapp array */
+    u32                                        in_map_num_entries;

-       /* value of the stored time */
-       unsigned long time_value;
-};
+    /* number of entries of the output mapp array */
+    u32                                        out_map_num_entries;

+#ifdef DX_CC52_SUPPORT

-/*
-  structure that represent one entry in the DMA LLI table
-*/
-struct sep_lli_entry_t {
-       /* physical address */
-       unsigned long physical_address;
+    /* major and minor device numbers for singleton */
+    dev_t                   singleton_device_number;
+
+    /* cdev struct for singleton */
+    struct cdev             singleton_cdev;
+
+    /* access flag for singleton */
+    unsigned long           singleton_access_flag;

-       /* block size */
-       unsigned long block_size;
+    /* caller id table */
+    struct sep_caller_id_entry
+                       caller_id_table[SEP_CALLER_ID_TABLE_NUM_ENTRIES];
+
+#endif /*DX_CC52_SUPPORT*/
  };

-/*
-  structure that reperesents data needed for lli table construction
-*/
-struct sep_lli_prepare_table_data_t {
-       /* pointer to the memory where the first lli entry to be built */
-       struct sep_lli_entry_t *lli_entry_ptr;

-       /* pointer to the array of lli entries from which the table is to b=
e built */
-       struct sep_lli_entry_t *lli_array_ptr;

-       /* number of elements in lli array */
-       int lli_array_size;
+#ifdef __LITTLE_ENDIAN

-       /* number of entries in the created table */
-       int num_table_entries;
+static inline void SEP_WRITE_REGISTER(struct device_context *dev,
+      int reg, u32 value)
+{
+       void __iomem *addr =3D dev->reg_addr + reg;
+       writel(value, addr);
+}

-       /* number of array entries processed during table creation */
-       int num_array_entries_processed;
+static inline u32 SEP_READ_REGISTER(struct device_context *dev, int reg)
+{
+       void __iomem *addr =3D dev->reg_addr + reg;
+       return readl(addr);
+}

-       /* the totatl data size in the created table */
-       int lli_table_total_data_size;
-};
+#define SEP_CHANGE_ENDIANNESS(val) (val)

-/*
-  structure that represent tone table - it is not used in code, jkust
-  to show what table looks like
-*/
-struct sep_lli_table_t {
-       /* number of pages mapped in this tables. If 0 - means that the tab=
le
-          is not defined (used as a valid flag) */
-       unsigned long num_pages;
-       /*
-          pointer to array of page pointers that represent the mapping of =
the
-          virtual buffer defined by the table to the physical memory. If t=
his
-          pointer is NULL, it means that the table is not defined
-          (used as a valid flag)
-        */
-       struct page **table_page_array_ptr;
-
-       /* maximum flow entries in table */
-       struct sep_lli_entry_t lli_entries[SEP_DRIVER_MAX_FLOW_NUM_ENTRIES_=
IN_TABLE];
-};

+#else

-/*
-  structure for keeping the mapping of the virtual buffer into physical pa=
ges
-*/
-struct sep_flow_buffer_data {
-       /* pointer to the array of page structs pointers to the pages of th=
e
-          virtual buffer */
-       struct page **page_array_ptr;
+static inline void SEP_WRITE_REGISTER(struct device_context *dev,
+      int reg,
+      u32 value)
+{
+       void __iomem *addr =3D dev->reg_addr + reg;
+       writel_be(value, addr);
+}

-       /* number of pages taken by the virtual buffer */
-       unsigned long num_pages;
+static inline u32 SEP_READ_REGISTER(struct device_context *dev, int reg)
+{
+       void __iomem *addr =3D dev->reg_addr + reg;
+       return readl_be(addr);
+}

-       /* this flag signals if this page_array is the last one among many =
that were
-          sent in one setting to SEP */
-       unsigned long last_page_array_flag;
-};
+#define SEP_CHANGE_ENDIANNESS(val) \
+      (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | \
+      (((val) & 0x0000FF00) << 8) | \
+      (((val) & 0x000000FF) << 24))

-/*
-  struct that keeps all the data for one flow
-*/
-struct sep_flow_context_t {
-       /*
-          work struct for handling the flow done interrupt in the workqueu=
e
-          this structure must be in the first place, since it will be used
-          forcasting to the containing flow context
-        */
-       struct work_struct flow_wq;
+#endif
+
+/* wait for SRAM write complete(indirect write */
+static inline void SEP_WAIT_SRAM_WRITE_COMPLETE(struct device_context *dev=
)
+{
+       u32  reg_val;
+       do {
+               reg_val =3D SEP_READ_REGISTER(dev, HW_SRAM_DATA_READY_REG_A=
DDR);
+       } while (!(reg_val & 0x1));
+}
+
+
+
+/*----------------------------------------------------------------
+  IOCTL command defines
+  -----------------------------------------------------------------*/

-       /* flow id */
-       unsigned long flow_id;
+/* magic number 1 of the sep IOCTL command */
+#define SEP_IOC_MAGIC_NUMBER                           's'

-       /* additional input tables exists */
-       unsigned long input_tables_flag;
+/* sends interrupt to sep that message is ready */
+#define SEP_IOCSENDSEPCOMMAND     \
+      _IO(SEP_IOC_MAGIC_NUMBER, 0)

-       /* additional output tables exists */
-       unsigned long output_tables_flag;
+/* sends interrupt to sep that message is ready */
+#define SEP_IOCSENDSEPRPLYCOMMAND     \
+      _IO(SEP_IOC_MAGIC_NUMBER, 1)

-       /*  data of the first input file */
-       struct sep_lli_entry_t first_input_table;
+/* allocate memory in data pool */
+#define SEP_IOCALLOCDATAPOLL      \
+      _IOW(SEP_IOC_MAGIC_NUMBER, 2, struct sep_driver_alloc_t)

-       /* data of the first output table */
-       struct sep_lli_entry_t first_output_table;
+/* write to pre-allocated  memory in data pool */
+#define SEP_IOCWRITEDATAPOLL      \
+      _IOW(SEP_IOC_MAGIC_NUMBER, 3, struct sep_driver_write_t)

-       /* last input table data */
-       struct sep_lli_entry_t last_input_table;
+/* read from  pre-allocated  memory in data pool */
+#define SEP_IOCREADDATAPOLL     \
+      _IOW(SEP_IOC_MAGIC_NUMBER, 4, struct sep_driver_write_t)

-       /* last output table data */
-       struct sep_lli_entry_t last_output_table;
+/* create sym dma lli tables */
+#define SEP_IOCCREATESYMDMATABLE      \
+      _IOW(SEP_IOC_MAGIC_NUMBER, 5, struct sep_driver_build_sync_table_t)

-       /* first list of table */
-       struct sep_lli_entry_t input_tables_in_process;
+/* create flow dma lli tables */
+#define SEP_IOCCREATEFLOWDMATABLE     \
+      _IO(SEP_IOC_MAGIC_NUMBER, 6)

-       /* output table in process (in sep) */
-       struct sep_lli_entry_t output_tables_in_process;
+/* free dynamic data aalocated during table creation */
+#define SEP_IOCFREEDMATABLEDATA     \
+      _IO(SEP_IOC_MAGIC_NUMBER , 7)

-       /* size of messages in bytes */
-       unsigned long message_size_in_bytes;
+/* get the static pool area addersses (physical and virtual) */
+#define SEP_IOCGETSTATICPOOLADDR      \
+      _IOR(SEP_IOC_MAGIC_NUMBER , 8, struct sep_driver_static_pool_addr_t)

-       /* message */
-       unsigned char message[SEP_MAX_ADD_MESSAGE_LENGTH_IN_BYTES];
-};
+/* set flow id command */
+#define SEP_IOCSETFLOWID      \
+      _IO(SEP_IOC_MAGIC_NUMBER , 9)
+
+/* add tables to the dynamic flow */
+#define SEP_IOCADDFLOWTABLE     \
+      _IO(SEP_IOC_MAGIC_NUMBER , 10)
+
+/* add flow add tables message */
+#define SEP_IOCADDFLOWMESSAGE     \
+      _IO(SEP_IOC_MAGIC_NUMBER , 11)
+
+/* start sep command */
+#define SEP_IOCSEPSTART     \
+      _IO(SEP_IOC_MAGIC_NUMBER , 12)
+
+/* init sep command */
+#define SEP_IOCSEPINIT      \
+      _IOW(SEP_IOC_MAGIC_NUMBER , 13 , struct sep_driver_init_t)
+
+/* end transaction command */
+#define SEP_IOCENDTRANSACTION     \
+      _IO(SEP_IOC_MAGIC_NUMBER , 15)
+
+/* reallocate cache and resident */
+#define SEP_IOCREALLOCCACHERES      \
+  _IOW(SEP_IOC_MAGIC_NUMBER, 16, struct sep_driver_realloc_cache_resident_=
t)
+
+/* get the offset of the address starting from the beginnnig of the map ar=
ea */
+#define SEP_IOCGETMAPPEDADDROFFSET      \
+      _IOR(SEP_IOC_MAGIC_NUMBER , 17 , struct sep_driver_get_mapped_offset=
_t)
+
+/* reallocate cache and resident */
+#define SEP_IOCREALLOCEXTCACHE      \
+      _IOW(SEP_IOC_MAGIC_NUMBER , 18 , struct sep_driver_realloc_ext_cache=
_t)
+
+/* get time address and value */
+#define SEP_IOCGETIME     \
+      _IOR(SEP_IOC_MAGIC_NUMBER , 19 , struct sep_driver_get_time_t)
+
+#define SEP_IOCRARPREPAREMESSAGE      \
+      _IOW(SEP_IOC_MAGIC_NUMBER , 20 , struct sep_driver_rar_handle_to_bus=
)
+
+#define SEP_IOCTLSINGLETONLOCK      \
+      _IO(SEP_IOC_MAGIC_NUMBER , 32)
+
+#define SEP_IOCTLSINGLETONUNLOCK      \
+      _IO(SEP_IOC_MAGIC_NUMBER , 33)
+
+#define SEP_IOCTLSETCALLERID      \
+      _IOW(SEP_IOC_MAGIC_NUMBER , 34 , struct sep_driver_set_caller_id_t)
+
+
+/*----------------------------------------------------------------
+  PUBLIC functions
+  -----------------------------------------------------------------*/
+
+/*
+  this function locks SEP by locking the semaphore
+*/
+int sep_lock(void);
+
+/*
+  this function unlocks SEP
+*/
+void sep_unlock(void);
+
+/*
+       this function returns the address of the message shared area
+*/
+void  *sep_map_shared_area(void);
+
+
+/*
+       this function returns the address of the message shared area
+*/
+int sep_send_msg_rdy_cmd(void);
+
+
+/*
+       This function builds input and output DMA tables for synhronic symm=
etric
+       operations (AES, DES) It also checks that each table is of the modu=
lar
+       block size
+*/
+int sep_prepare_input_output_dma_table(unsigned long   app_virt_in_addr,
+                               unsigned long   app_virt_out_addr,
+                               u32   data_size,
+                               u32   block_size,
+                               dma_addr_t  *lli_table_in_ptr,
+                               dma_addr_t  *lli_table_out_ptr,
+                               u32  *in_num_entries_ptr,
+                               u32  *out_num_entries_ptr,
+                               u32  *table_data_size_ptr,
+                               bool            isKernelVirtualAddress);
+
+/*
+       This function prepares only input DMA table for synhronic symmetric
+       operations (HASH)
+*/
+int sep_prepare_input_dma_table(unsigned long   app_virt_addr,
+                               u32   data_size,
+                               u32   block_size,
+                               dma_addr_t  *lli_table_ptr,
+                               u32  *num_entries_ptr,
+                               u32  *table_data_size_ptr,
+                               bool            isKernelVirtualAddress);
+
+/* poll(suspend) , until reply from sep */
+int sep_driver_poll(u32 *source_ptr);
+
+/*
+       this function handles the request for freeing dma table for
+       synhronic actions
+*/
+int sep_free_dma_table_data_handler(void);


  #endif
diff --git a/drivers/staging/sep/sep_driver_config.h b/drivers/staging/sep/=
sep_driver_config.h
index 6008fe5..0ae168d 100644
--- a/drivers/staging/sep/sep_driver_config.h
+++ b/drivers/staging/sep/sep_driver_config.h
@@ -1,23 +1,29 @@
-/*
- *
- *  sep_driver_config.h - Security Processor Driver configuration
- *
- *  Copyright(c) 2009 Intel Corporation. All rights reserved.
- *  Copyright(c) 2009 Discretix. All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify i=
t
- *  under the terms of the GNU General Public License as published by the =
Free
- *  Software Foundation; either version 2 of the License, or (at your opti=
on)
- *  any later version.
+ /*
+ * sep_driver_config.h
   *
- *  This program is distributed in the hope that it will be useful, but WI=
THOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License =
for
- *  more details.
- *
- *  You should have received a copy of the GNU General Public License alon=
g with
- *  this program; if not, write to the Free Software Foundation, Inc., 59
- *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *************************************************************************=
*
+ *   Copyright 2009 (c) Discretix Technologies Ltd.                       =
   *
+ *   Copyright 2009 (c) Intel Corporation                                 =
   *
+ *                                                                        =
 *
+ *   This software is protected by copyright, international treaties and  =
 *
+ *   various patents. Any copy or reproduction of this Software as        =
 *
+ *   permitted below, must include this Copyright Notice as well as any   =
 *
+ *   other notices provided under such license.                           =
 *
+ *                                                                        =
 *
+ *   This program shall be governed by, and may be used and redistributed =
 *
+ *   under the terms and conditions of the GNU General Public License,    =
 *
+ *   version 2, as published by the Free Software Foundation.             =
 *
+ *                                                                        =
 *
+ *   This program is distributed in the hope that it will be useful,      =
 *
+ *   but WITHOUT ANY liability and WARRANTY; without even the implied     =
 *
+ *   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     =
 *
+ *   See the GNU General Public License for more details.                 =
 *
+ *                                                                        =
 *
+ *   You should have received a copy of the GNU General Public License    =
 *
+ *   along with this program; if not, please write to the Free Software   =
 *
+ *   Foundation, Inc.,                                                    =
 *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.            =
 *
+ *************************************************************************=
*
   *
   *  CONTACTS:
   *
@@ -25,10 +31,9 @@
   *
   *  CHANGES:
   *
- *  2009.06.26 Initial publish
+ *  2010.01.08 Initial publish
   *
   */
-
  #ifndef __SEP_DRIVER_CONFIG_H__
  #define __SEP_DRIVER_CONFIG_H__

@@ -39,7 +44,7 @@

  /* if flag is on , then the driver is running in polling and
        not interrupt mode */
-#define SEP_DRIVER_POLLING_MODE                         1
+#define SEP_DRIVER_POLLING_MODE                         0

  /* flag which defines if the shared area address should be
        reconfiged (send to SEP anew) during init of the driver */
@@ -48,10 +53,24 @@
  /* the mode for running on the ARM1172 Evaluation platform (flag is 1) */
  #define SEP_DRIVER_ARM_DEBUG_MODE                       0

+/* the mode for running on the PowerPC Evaluation platform (flag is 1) */
+#define SEP_DRIVER_PPC_DEBUG_MODE                       0
+
+/* RAR lock mode - cahce, resident and ext cache must be copied to externa=
l RAR
+   and locked by driver in the same API */
+#define SEP_DRIVER_LOCK_RAR_MODE                        0
+
+/* flag which defines if the SEP driver should config the OTP (flag is 1),
+   or not (flag is 0) */
+#define SEP_DRIVER_CONFIG_OTP                           1
+
  /*-------------------------------------------
        INTERNAL DATA CONFIGURATION
        -------------------------------------------*/

+/* the dirver name */
+#define DRIVER_NAME "sep_sec_driver"
+
  /* flag for the input array */
  #define SEP_DRIVER_IN_FLAG                              0

@@ -61,6 +80,13 @@
  /* maximum number of entries in one LLI tables */
  #define SEP_DRIVER_ENTRIES_PER_TABLE_IN_SEP             8

+/* flag that signifies tah the lock is
+currently held by the proccess (struct file) */
+#define SEP_DRIVER_OWN_LOCK_FLAG                        1
+
+/* flag that signifies tah the lock is currently NOT
+held by the proccess (struct file) */
+#define SEP_DRIVER_DISOWN_LOCK_FLAG                     0

  /*--------------------------------------------------------
        SHARED AREA  memory total size is 36K
@@ -82,6 +108,10 @@
        it is divided as following:

        TIME_MEMORY_AREA                     8B
+
+       RAR_MEMORY_AREA                      8B
+
+    CURRENT_CALLER_ID_MEMORY             70B
  -----------------------------------------------------------*/


@@ -104,13 +134,17 @@
  /* the size of the message shared area in pages */
  #define SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_SIZE_IN_BYTES   (1024 * 5)

-
  /* the size of the data pool shared area size in pages */
  #define SEP_DRIVER_FLOW_DMA_TABLES_AREA_SIZE_IN_BYTES         (1024 * 4)

  /* system data (time, caller id etc') pool */
-#define SEP_DRIVER_SYSTEM_DATA_MEMORY_SIZE_IN_BYTES           100
+#define SEP_DRIVER_SYSTEM_DATA_MEMORY_SIZE_IN_BYTES           (1024 * 3)
+
+/* the size in bytes of the time memory */
+#define SEP_DRIVER_TIME_MEMORY_SIZE_IN_BYTES                  8

+/* the size in bytes of the RAR parameters memory */
+#define SEP_DRIVER_SYSTEM_RAR_MEMORY_SIZE_IN_BYTES            8

  /* area size that is mapped  - we map the MESSAGE AREA, STATIC POOL and
        DATA POOL areas. area must be module 4k */
@@ -152,10 +186,23 @@
  #define SEP_DRIVER_SYSTEM_TIME_MEMORY_OFFSET_IN_BYTES \
        (SEP_DRIVER_SYSTEM_DATA_MEMORY_OFFSET_IN_BYTES)

+/* offset of the RAR area */
+#define SEP_DRIVER_SYSTEM_RAR_MEMORY_OFFSET_IN_BYTES \
+       (SEP_DRIVER_SYSTEM_TIME_MEMORY_OFFSET_IN_BYTES + \
+       SEP_DRIVER_TIME_MEMORY_SIZE_IN_BYTES)
+
+/* offset of the caller id area */
+#define SEP_DRIVER_SYSTEM_CALLER_ID_MEMORY_OFFSET_IN_BYTES \
+       (SEP_DRIVER_SYSTEM_RAR_MEMORY_OFFSET_IN_BYTES + \
+    SEP_DRIVER_SYSTEM_RAR_MEMORY_SIZE_IN_BYTES)


  /* start physical address of the SEP registers memory in HOST */
-#define SEP_IO_MEM_REGION_START_ADDRESS                       0x80000000
+#if SEP_DRIVER_PPC_DEBUG_MODE
+  #define SEP_IO_MEM_REGION_START_ADDRESS                       0x83F00000
+#else
+  #define SEP_IO_MEM_REGION_START_ADDRESS                       0x80000000
+#endif

  /* size of the SEP registers memory region  in HOST (for now 100 register=
s) */
  #define SEP_IO_MEM_REGION_SIZE                                (2 * 0x1000=
00)
@@ -184,42 +231,53 @@
  /* mask for entries after being shifted left */
  #define SEP_NUM_ENTRIES_MASK                                  0x7F

-/* default flow id */
-#define SEP_FREE_FLOW_ID                                      0xFFFFFFFF
-
-/* temp flow id used during cretiong of new flow until receiving
-       real flow id from sep */
-#define SEP_TEMP_FLOW_ID                   (SEP_DRIVER_NUM_FLOWS + 1)
-
-/* maximum add buffers message length in bytes */
-#define SEP_MAX_ADD_MESSAGE_LENGTH_IN_BYTES                   (7 * 4)
-
  /* maximum number of concurrent virtual buffers */
  #define SEP_MAX_VIRT_BUFFERS_CONCURRENT                       100

  /* the token that defines the start of time address */
  #define SEP_TIME_VAL_TOKEN                                    0x12345678

+/* size of the caller id hash (sha2) */
+#define SEP_CALLER_ID_HASH_SIZE_IN_BYTES                      32
+
+/* maximum number of entries in the caller id table */
+#define SEP_CALLER_ID_TABLE_NUM_ENTRIES                       20
+
+/* the token that defines the start of time address */
+#define SEP_RAR_VAL_TOKEN                                     0xABABABAB
+
+/* ioctl error that should be returned when trying
+   to realloc the cache/resident second time */
+#define SEP_ALREADY_INITIALIZED_ERR                           12
+
+/* bit that locks access to the shared area */
+#define SEP_MMAP_LOCK_BIT                                     0
+
+/* bit that lock access to the poll  - after send_command */
+#define SEP_SEND_MSG_LOCK_BIT                                 1
+
  /* DEBUG LEVEL MASKS */
  #define SEP_DEBUG_LEVEL_BASIC       0x1

+#define SEP_DEBUG_LEVEL_REGISTERS   0x2
+
  #define SEP_DEBUG_LEVEL_EXTENDED    0x4


-/* Debug helpers */
+/* FUNCTIONAL MACROS */

  #define dbg(fmt, args...) \
  do {\
-       if (debug & SEP_DEBUG_LEVEL_BASIC) \
+       if (sep_debug & SEP_DEBUG_LEVEL_BASIC) \
                printk(KERN_DEBUG fmt, ##args); \
-} while(0);
+} while (0);

  #define edbg(fmt, args...) \
  do { \
-       if (debug & SEP_DEBUG_LEVEL_EXTENDED) \
+       if (sep_debug & SEP_DEBUG_LEVEL_EXTENDED) \
                printk(KERN_DEBUG fmt, ##args); \
-} while(0);
+} while (0);



-#endif
+#endif /*__SEP_DRIVER_CONFIG_H__*/
diff --git a/drivers/staging/sep/sep_driver_ext_api.h b/drivers/staging/sep=
/sep_driver_ext_api.h
new file mode 100644
index 0000000..220164b
--- /dev/null
+++ b/drivers/staging/sep/sep_driver_ext_api.h
@@ -0,0 +1,127 @@
+/*
+ * sep_driver_ext_api.h
+ *
+ *************************************************************************=
*
+ *   Copyright 2009 (c) Discretix Technologies Ltd.                       =
   *
+ *   Copyright 2009 (c) Intel Corporation                                 =
   *
+ *                                                                        =
 *
+ *   This software is protected by copyright, international treaties and  =
 *
+ *   various patents. Any copy or reproduction of this Software as        =
 *
+ *   permitted below, must include this Copyright Notice as well as any   =
 *
+ *   other notices provided under such license.                           =
 *
+ *                                                                        =
 *
+ *   This program shall be governed by, and may be used and redistributed =
 *
+ *   under the terms and conditions of the GNU General Public License,    =
 *
+ *   version 2, as published by the Free Software Foundation.             =
 *
+ *                                                                        =
 *
+ *   This program is distributed in the hope that it will be useful,      =
 *
+ *   but WITHOUT ANY liability and WARRANTY; without even the implied     =
 *
+ *   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     =
 *
+ *   See the GNU General Public License for more details.                 =
 *
+ *                                                                        =
 *
+ *   You should have received a copy of the GNU General Public License    =
 *
+ *   along with this program; if not, please write to the Free Software   =
 *
+ *   Foundation, Inc.,                                                    =
 *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.            =
 *
+ *************************************************************************=
*
+ *
+ *  CONTACTS:
+ *
+ *  Mark Allyn         mark.a.allyn@xxxxxxxxx
+ *
+ *  CHANGES:
+ *
+ *  2010.01.08 Initial publish
+ *
+ */
+
+#ifndef __SEP_DRIVER_EXT_API_H__
+#define __SEP_DRIVER_EXT_API_H__
+
+
+/*
+This functions locks the area of the resident and cache sep code (if possi=
ble)
+*/
+int sep_lock_cache_resident_area(void);
+
+/*
+This functions copies the cache and resident from their source location in=
to
+destination memory, which is external to Linux VM and is given as physical
+address
+*/
+int sep_copy_cache_resident_to_area(struct device_context *sep_context_ptr=
,
+      dma_addr_t  *dst_new_cache_addr_ptr,
+      dma_addr_t  *dst_new_resident_addr_ptr,
+      dma_addr_t  *dst_new_dcache_addr_ptr);
+
+/*
+  This functions copies the external cache (3rd party) from
+  it's source location into destination memory,
+  which is external to Linux VM and is given as physical address.
+  It is supposed to be adjustent to the i-cache boundary
+*/
+int sep_copy_ext_cache_to_area(void *src_ext_cache_addr,
+      u32   ext_cache_size_in_bytes,
+      dma_addr_t  *ext_cache_bus_addr_ptr);
+
+
+
+/*
+This functions maps and allocates the shared area on the external
+RAM (device) The input is shared_area_size - the size of the memory
+to allocate. The outputs are kernel_shared_area_addr_ptr - the kerenl
+address of the mapped and allocated shared area, and
+phys_shared_area_addr_ptr - the physical address of the shared area
+*/
+int sep_map_and_alloc_shared_area(struct device_context *sep_context_ptr);
+
+/*
+This functions unmaps and deallocates the shared area on the  external
+RAM (device) The input is shared_area_size - the size of the memory to
+deallocate,kernel_shared_area_addr_ptr - the kernel address of the
+mapped and allocated shared area,phys_shared_area_addr_ptr - the physical
+address of the shared area
+*/
+void sep_unmap_and_free_shared_area(struct device_context *sep_context_ptr=
);
+
+
+/*
+This functions returns the physical address inside shared area according
+to the virtual address. It can be either on the externa RAM device
+(ioremapped), or on the system RAM
+*/
+dma_addr_t sep_shared_area_virt_to_bus(struct device_context *sep_context_=
ptr,
+      void  *virt_address);
+
+/*
+This functions returns the vitrual address inside shared area according
+to the physical address. It can be either on the externa RAM device
+(ioremapped), or on the system RAM This implementation is for the external=
 RAM
+*/
+void  *sep_shared_area_bus_to_virt(struct device_context *sep_context_ptr,
+      dma_addr_t bus_address);
+
+/*
+This function registers th driver to the device
+subsystem (either PCI, USB, etc)
+*/
+int sep_register_driver_to_device(void);
+
+/*
+This function translates the RAR handle into the bus address
+*/
+int sep_rar_handle_to_bus(void *rar_handle , dma_addr_t *rar_bus);
+
+extern struct device_context sep_context;
+
+/*
+Interrupt handler
+*/
+irqreturn_t sep_inthandler(int irq, void *dev_id);
+
+/*
+Callback to be used to furnish addresses when ready
+*/
+int sep_callback(void *sep_context_pointer);
+
+#endif /*__SEP_DRIVER_EXT_API_H__*/
diff --git a/drivers/staging/sep/sep_driver_hw_defs.h b/drivers/staging/sep=
/sep_driver_hw_defs.h
index ea6abd8..b571256 100644
--- a/drivers/staging/sep/sep_driver_hw_defs.h
+++ b/drivers/staging/sep/sep_driver_hw_defs.h
@@ -1,23 +1,29 @@
  /*
+ * sep_driver_hw_defs.h
   *
- *  sep_driver_hw_defs.h - Security Processor Driver hardware definitions
- *
- *  Copyright(c) 2009 Intel Corporation. All rights reserved.
- *  Copyright(c) 2009 Discretix. All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify i=
t
- *  under the terms of the GNU General Public License as published by the =
Free
- *  Software Foundation; either version 2 of the License, or (at your opti=
on)
- *  any later version.
- *
- *  This program is distributed in the hope that it will be useful, but WI=
THOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License =
for
- *  more details.
- *
- *  You should have received a copy of the GNU General Public License alon=
g with
- *  this program; if not, write to the Free Software Foundation, Inc., 59
- *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *************************************************************************=
*
+ *   Copyright 2009 (c) Discretix Technologies Ltd.                       =
   *
+ *   Copyright 2009 (c) Intel Corporation                                 =
   *
+ *                                                                        =
 *
+ *   This software is protected by copyright, international treaties and  =
 *
+ *   various patents. Any copy or reproduction of this Software as        =
 *
+ *   permitted below, must include this Copyright Notice as well as any   =
 *
+ *   other notices provided under such license.                           =
 *
+ *                                                                        =
 *
+ *   This program shall be governed by, and may be used and redistributed =
 *
+ *   under the terms and conditions of the GNU General Public License,    =
 *
+ *   version 2, as published by the Free Software Foundation.             =
 *
+ *                                                                        =
 *
+ *   This program is distributed in the hope that it will be useful,      =
 *
+ *   but WITHOUT ANY liability and WARRANTY; without even the implied     =
 *
+ *   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     =
 *
+ *   See the GNU General Public License for more details.                 =
 *
+ *                                                                        =
 *
+ *   You should have received a copy of the GNU General Public License    =
 *
+ *   along with this program; if not, please write to the Free Software   =
 *
+ *   Foundation, Inc.,                                                    =
 *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.            =
 *
+ *************************************************************************=
*
   *
   *  CONTACTS:
   *
@@ -25,7 +31,7 @@
   *
   *  CHANGES:
   *
- *  2009.06.26 Initial publish
+ *  2010.01.08 Initial publish
   *
   */

@@ -39,194 +45,202 @@
  /*       DO NOT EDIT THIS FILE !!!                                       =
   */
  /*-----------------------------------------------------------------------=
---*/

+#ifdef __cplusplus
+extern "C"
+{
+#endif

  /* cf registers */
-#define         HW_R0B_ADDR_0_REG_ADDR                  0x0000UL
-#define         HW_R0B_ADDR_1_REG_ADDR                  0x0004UL
-#define         HW_R0B_ADDR_2_REG_ADDR                  0x0008UL
-#define         HW_R0B_ADDR_3_REG_ADDR                  0x000cUL
-#define         HW_R0B_ADDR_4_REG_ADDR                  0x0010UL
-#define         HW_R0B_ADDR_5_REG_ADDR                  0x0014UL
-#define         HW_R0B_ADDR_6_REG_ADDR                  0x0018UL
-#define         HW_R0B_ADDR_7_REG_ADDR                  0x001cUL
-#define         HW_R0B_ADDR_8_REG_ADDR                  0x0020UL
-#define         HW_R2B_ADDR_0_REG_ADDR                  0x0080UL
-#define         HW_R2B_ADDR_1_REG_ADDR                  0x0084UL
-#define         HW_R2B_ADDR_2_REG_ADDR                  0x0088UL
-#define         HW_R2B_ADDR_3_REG_ADDR                  0x008cUL
-#define         HW_R2B_ADDR_4_REG_ADDR                  0x0090UL
-#define         HW_R2B_ADDR_5_REG_ADDR                  0x0094UL
-#define         HW_R2B_ADDR_6_REG_ADDR                  0x0098UL
-#define         HW_R2B_ADDR_7_REG_ADDR                  0x009cUL
-#define         HW_R2B_ADDR_8_REG_ADDR                  0x00a0UL
-#define         HW_R3B_REG_ADDR                         0x00C0UL
-#define         HW_R4B_REG_ADDR                         0x0100UL
-#define         HW_CSA_ADDR_0_REG_ADDR                  0x0140UL
-#define         HW_CSA_ADDR_1_REG_ADDR                  0x0144UL
-#define         HW_CSA_ADDR_2_REG_ADDR                  0x0148UL
-#define         HW_CSA_ADDR_3_REG_ADDR                  0x014cUL
-#define         HW_CSA_ADDR_4_REG_ADDR                  0x0150UL
-#define         HW_CSA_ADDR_5_REG_ADDR                  0x0154UL
-#define         HW_CSA_ADDR_6_REG_ADDR                  0x0158UL
-#define         HW_CSA_ADDR_7_REG_ADDR                  0x015cUL
-#define         HW_CSA_ADDR_8_REG_ADDR                  0x0160UL
-#define         HW_CSA_REG_ADDR                         0x0140UL
-#define         HW_SINB_REG_ADDR                        0x0180UL
-#define         HW_SOUTB_REG_ADDR                       0x0184UL
-#define         HW_PKI_CONTROL_REG_ADDR                 0x01C0UL
-#define         HW_PKI_STATUS_REG_ADDR                  0x01C4UL
-#define         HW_PKI_BUSY_REG_ADDR                0x01C8UL
-#define         HW_PKI_A_1025_REG_ADDR                  0x01CCUL
-#define         HW_PKI_SDMA_CTL_REG_ADDR                0x01D0UL
-#define         HW_PKI_SDMA_OFFSET_REG_ADDR     0x01D4UL
-#define         HW_PKI_SDMA_POINTERS_REG_ADDR   0x01D8UL
-#define         HW_PKI_SDMA_DLENG_REG_ADDR              0x01DCUL
-#define         HW_PKI_SDMA_EXP_POINTERS_REG_ADDR       0x01E0UL
-#define         HW_PKI_SDMA_RES_POINTERS_REG_ADDR       0x01E4UL
-#define         HW_PKI_CLR_REG_ADDR                     0x01E8UL
-#define         HW_PKI_SDMA_BUSY_REG_ADDR                   0x01E8UL
-#define         HW_PKI_SDMA_FIRST_EXP_N_REG_ADDR        0x01ECUL
-#define         HW_PKI_SDMA_MUL_BY1_REG_ADDR            0x01F0UL
-#define         HW_PKI_SDMA_RMUL_SEL_REG_ADDR           0x01F4UL
-#define         HW_DES_KEY_0_REG_ADDR                   0x0208UL
-#define         HW_DES_KEY_1_REG_ADDR                   0x020CUL
-#define         HW_DES_KEY_2_REG_ADDR                   0x0210UL
-#define         HW_DES_KEY_3_REG_ADDR                   0x0214UL
-#define         HW_DES_KEY_4_REG_ADDR                   0x0218UL
-#define         HW_DES_KEY_5_REG_ADDR                   0x021CUL
-#define         HW_DES_CONTROL_0_REG_ADDR               0x0220UL
-#define         HW_DES_CONTROL_1_REG_ADDR               0x0224UL
-#define         HW_DES_IV_0_REG_ADDR                    0x0228UL
-#define         HW_DES_IV_1_REG_ADDR                    0x022CUL
-#define         HW_AES_KEY_0_ADDR_0_REG_ADDR            0x0400UL
-#define         HW_AES_KEY_0_ADDR_1_REG_ADDR            0x0404UL
-#define         HW_AES_KEY_0_ADDR_2_REG_ADDR            0x0408UL
-#define         HW_AES_KEY_0_ADDR_3_REG_ADDR            0x040cUL
-#define         HW_AES_KEY_0_ADDR_4_REG_ADDR            0x0410UL
-#define         HW_AES_KEY_0_ADDR_5_REG_ADDR            0x0414UL
-#define         HW_AES_KEY_0_ADDR_6_REG_ADDR            0x0418UL
-#define         HW_AES_KEY_0_ADDR_7_REG_ADDR            0x041cUL
-#define         HW_AES_KEY_0_REG_ADDR                   0x0400UL
-#define         HW_AES_IV_0_ADDR_0_REG_ADDR             0x0440UL
-#define         HW_AES_IV_0_ADDR_1_REG_ADDR             0x0444UL
-#define         HW_AES_IV_0_ADDR_2_REG_ADDR             0x0448UL
-#define         HW_AES_IV_0_ADDR_3_REG_ADDR             0x044cUL
-#define         HW_AES_IV_0_REG_ADDR                    0x0440UL
-#define         HW_AES_CTR1_ADDR_0_REG_ADDR             0x0460UL
-#define         HW_AES_CTR1_ADDR_1_REG_ADDR             0x0464UL
-#define         HW_AES_CTR1_ADDR_2_REG_ADDR             0x0468UL
-#define         HW_AES_CTR1_ADDR_3_REG_ADDR             0x046cUL
-#define         HW_AES_CTR1_REG_ADDR                    0x0460UL
-#define         HW_AES_SK_REG_ADDR                      0x0478UL
-#define         HW_AES_MAC_OK_REG_ADDR                      0x0480UL
-#define         HW_AES_PREV_IV_0_ADDR_0_REG_ADDR        0x0490UL
-#define         HW_AES_PREV_IV_0_ADDR_1_REG_ADDR        0x0494UL
-#define         HW_AES_PREV_IV_0_ADDR_2_REG_ADDR        0x0498UL
-#define         HW_AES_PREV_IV_0_ADDR_3_REG_ADDR        0x049cUL
-#define         HW_AES_PREV_IV_0_REG_ADDR                   0x0490UL
-#define         HW_AES_CONTROL_REG_ADDR                     0x04C0UL
-#define         HW_HASH_H0_REG_ADDR                 0x0640UL
-#define         HW_HASH_H1_REG_ADDR                 0x0644UL
-#define         HW_HASH_H2_REG_ADDR                 0x0648UL
-#define         HW_HASH_H3_REG_ADDR                 0x064CUL
-#define         HW_HASH_H4_REG_ADDR                 0x0650UL
-#define         HW_HASH_H5_REG_ADDR                 0x0654UL
-#define         HW_HASH_H6_REG_ADDR                 0x0658UL
-#define         HW_HASH_H7_REG_ADDR                 0x065CUL
-#define         HW_HASH_H8_REG_ADDR                 0x0660UL
-#define         HW_HASH_H9_REG_ADDR                 0x0664UL
-#define         HW_HASH_H10_REG_ADDR                0x0668UL
-#define         HW_HASH_H11_REG_ADDR                0x066CUL
-#define         HW_HASH_H12_REG_ADDR                0x0670UL
-#define         HW_HASH_H13_REG_ADDR                0x0674UL
-#define         HW_HASH_H14_REG_ADDR                0x0678UL
-#define         HW_HASH_H15_REG_ADDR                0x067CUL
-#define         HW_HASH_CONTROL_REG_ADDR                0x07C0UL
-#define         HW_HASH_PAD_EN_REG_ADDR                 0x07C4UL
-#define         HW_HASH_PAD_CFG_REG_ADDR                0x07C8UL
-#define         HW_HASH_CUR_LEN_0_REG_ADDR      0x07CCUL
-#define         HW_HASH_CUR_LEN_1_REG_ADDR      0x07D0UL
-#define         HW_HASH_CUR_LEN_2_REG_ADDR      0x07D4UL
-#define         HW_HASH_CUR_LEN_3_REG_ADDR      0x07D8UL
-#define         HW_HASH_PARAM_REG_ADDR                  0x07DCUL
-#define         HW_HASH_INT_BUSY_REG_ADDR               0x07E0UL
-#define         HW_HASH_SW_RESET_REG_ADDR               0x07E4UL
-#define         HW_HASH_ENDIANESS_REG_ADDR      0x07E8UL
-#define         HW_HASH_DATA_REG_ADDR               0x07ECUL
-#define         HW_DRNG_CONTROL_REG_ADDR                0x0800UL
-#define         HW_DRNG_VALID_REG_ADDR                  0x0804UL
-#define         HW_DRNG_DATA_REG_ADDR               0x0808UL
-#define         HW_RND_SRC_EN_REG_ADDR                  0x080CUL
-#define         HW_AES_CLK_ENABLE_REG_ADDR      0x0810UL
-#define         HW_DES_CLK_ENABLE_REG_ADDR      0x0814UL
-#define         HW_HASH_CLK_ENABLE_REG_ADDR     0x0818UL
-#define         HW_PKI_CLK_ENABLE_REG_ADDR      0x081CUL
-#define         HW_CLK_STATUS_REG_ADDR                  0x0824UL
-#define         HW_CLK_ENABLE_REG_ADDR                  0x0828UL
-#define         HW_DRNG_SAMPLE_REG_ADDR                 0x0850UL
-#define         HW_RND_SRC_CTL_REG_ADDR                 0x0858UL
-#define         HW_CRYPTO_CTL_REG_ADDR                  0x0900UL
-#define         HW_CRYPTO_STATUS_REG_ADDR               0x090CUL
-#define         HW_CRYPTO_BUSY_REG_ADDR                 0x0910UL
-#define         HW_AES_BUSY_REG_ADDR                0x0914UL
-#define         HW_DES_BUSY_REG_ADDR                0x0918UL
-#define         HW_HASH_BUSY_REG_ADDR               0x091CUL
-#define         HW_CONTENT_REG_ADDR                 0x0924UL
-#define         HW_VERSION_REG_ADDR                 0x0928UL
-#define         HW_CONTEXT_ID_REG_ADDR                  0x0930UL
-#define         HW_DIN_BUFFER_REG_ADDR                  0x0C00UL
-#define         HW_DIN_MEM_DMA_BUSY_REG_ADDR    0x0c20UL
-#define         HW_SRC_LLI_MEM_ADDR_REG_ADDR    0x0c24UL
-#define         HW_SRC_LLI_WORD0_REG_ADDR               0x0C28UL
-#define         HW_SRC_LLI_WORD1_REG_ADDR               0x0C2CUL
-#define         HW_SRAM_SRC_ADDR_REG_ADDR               0x0c30UL
-#define         HW_DIN_SRAM_BYTES_LEN_REG_ADDR  0x0c34UL
-#define         HW_DIN_SRAM_DMA_BUSY_REG_ADDR   0x0C38UL
-#define         HW_WRITE_ALIGN_REG_ADDR                 0x0C3CUL
-#define         HW_OLD_DATA_REG_ADDR                0x0C48UL
-#define         HW_WRITE_ALIGN_LAST_REG_ADDR    0x0C4CUL
-#define         HW_DOUT_BUFFER_REG_ADDR                 0x0C00UL
-#define         HW_DST_LLI_WORD0_REG_ADDR               0x0D28UL
-#define         HW_DST_LLI_WORD1_REG_ADDR               0x0D2CUL
-#define         HW_DST_LLI_MEM_ADDR_REG_ADDR    0x0D24UL
-#define         HW_DOUT_MEM_DMA_BUSY_REG_ADDR   0x0D20UL
-#define         HW_SRAM_DEST_ADDR_REG_ADDR      0x0D30UL
-#define         HW_DOUT_SRAM_BYTES_LEN_REG_ADDR 0x0D34UL
-#define         HW_DOUT_SRAM_DMA_BUSY_REG_ADDR  0x0D38UL
-#define         HW_READ_ALIGN_REG_ADDR                  0x0D3CUL
-#define         HW_READ_LAST_DATA_REG_ADDR      0x0D44UL
-#define         HW_RC4_THRU_CPU_REG_ADDR                0x0D4CUL
-#define         HW_AHB_SINGLE_REG_ADDR                  0x0E00UL
-#define         HW_SRAM_DATA_REG_ADDR               0x0F00UL
-#define         HW_SRAM_ADDR_REG_ADDR               0x0F04UL
-#define         HW_SRAM_DATA_READY_REG_ADDR     0x0F08UL
-#define         HW_HOST_IRR_REG_ADDR                     0x0A00UL
-#define         HW_HOST_IMR_REG_ADDR                     0x0A04UL
-#define         HW_HOST_ICR_REG_ADDR                     0x0A08UL
-#define         HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR  0x0A10UL
-#define         HW_HOST_SEP_BUSY_REG_ADDR                    0x0A14UL
-#define         HW_HOST_SEP_LCS_REG_ADDR                     0x0A18UL
-#define         HW_HOST_CC_SW_RST_REG_ADDR               0x0A40UL
-#define         HW_HOST_SEP_SW_RST_REG_ADDR              0x0A44UL
-#define         HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR        0x0A80UL
-#define         HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR        0x0A84UL
-#define         HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR        0x0A88UL
-#define         HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR        0x0A8cUL
-#define         HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR        0x0A90UL
-#define         HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR        0x0A94UL
-#define         HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR    0x0A98UL
-#define         HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR        0x0A9cUL
-#define         HW_HOST_SEP_HOST_GPR0_REG_ADDR           0x0B00UL
-#define         HW_HOST_SEP_HOST_GPR1_REG_ADDR           0x0B04UL
-#define         HW_HOST_SEP_HOST_GPR2_REG_ADDR           0x0B08UL
-#define         HW_HOST_SEP_HOST_GPR3_REG_ADDR       0x0B0CUL
-#define         HW_HOST_HOST_SEP_GPR0_REG_ADDR       0x0B80UL
-#define         HW_HOST_HOST_SEP_GPR1_REG_ADDR       0x0B84UL
-#define         HW_HOST_HOST_SEP_GPR2_REG_ADDR       0x0B88UL
-#define         HW_HOST_HOST_SEP_GPR3_REG_ADDR       0x0B8CUL
-#define         HW_HOST_HOST_ENDIAN_REG_ADDR         0x0B90UL
-#define         HW_HOST_HOST_COMM_CLK_EN_REG_ADDR        0x0B94UL
-#define         HW_CLR_SRAM_BUSY_REG_REG_ADDR        0x0F0CUL
+#define         HW_R0B_ADDR_0_REG_ADDR          0x0000UL
+#define         HW_R0B_ADDR_1_REG_ADDR          0x0004UL
+#define         HW_R0B_ADDR_2_REG_ADDR          0x0008UL
+#define         HW_R0B_ADDR_3_REG_ADDR          0x000cUL
+#define         HW_R0B_ADDR_4_REG_ADDR          0x0010UL
+#define         HW_R0B_ADDR_5_REG_ADDR          0x0014UL
+#define         HW_R0B_ADDR_6_REG_ADDR          0x0018UL
+#define         HW_R0B_ADDR_7_REG_ADDR          0x001cUL
+#define         HW_R0B_ADDR_8_REG_ADDR          0x0020UL
+#define         HW_R2B_ADDR_0_REG_ADDR          0x0080UL
+#define         HW_R2B_ADDR_1_REG_ADDR          0x0084UL
+#define         HW_R2B_ADDR_2_REG_ADDR          0x0088UL
+#define         HW_R2B_ADDR_3_REG_ADDR          0x008cUL
+#define         HW_R2B_ADDR_4_REG_ADDR          0x0090UL
+#define         HW_R2B_ADDR_5_REG_ADDR          0x0094UL
+#define         HW_R2B_ADDR_6_REG_ADDR          0x0098UL
+#define         HW_R2B_ADDR_7_REG_ADDR          0x009cUL
+#define         HW_R2B_ADDR_8_REG_ADDR          0x00a0UL
+#define         HW_R3B_REG_ADDR                         0x00C0UL
+#define         HW_R4B_REG_ADDR                         0x0100UL
+#define         HW_CSA_ADDR_0_REG_ADDR          0x0140UL
+#define         HW_CSA_ADDR_1_REG_ADDR          0x0144UL
+#define         HW_CSA_ADDR_2_REG_ADDR          0x0148UL
+#define         HW_CSA_ADDR_3_REG_ADDR          0x014cUL
+#define         HW_CSA_ADDR_4_REG_ADDR          0x0150UL
+#define         HW_CSA_ADDR_5_REG_ADDR          0x0154UL
+#define         HW_CSA_ADDR_6_REG_ADDR          0x0158UL
+#define         HW_CSA_ADDR_7_REG_ADDR          0x015cUL
+#define         HW_CSA_ADDR_8_REG_ADDR          0x0160UL
+#define         HW_CSA_REG_ADDR                         0x0140UL
+#define         HW_SINB_REG_ADDR                        0x0180UL
+#define         HW_SOUTB_REG_ADDR                       0x0184UL
+#define         HW_PKI_CONTROL_REG_ADDR                 0x01C0UL
+#define         HW_PKI_STATUS_REG_ADDR          0x01C4UL
+#define         HW_PKI_BUSY_REG_ADDR                0x01C8UL
+#define         HW_PKI_A_1025_REG_ADDR          0x01CCUL
+#define         HW_PKI_SDMA_CTL_REG_ADDR                0x01D0UL
+#define         HW_PKI_SDMA_OFFSET_REG_ADDR     0x01D4UL
+#define         HW_PKI_SDMA_POINTERS_REG_ADDR   0x01D8UL
+#define         HW_PKI_SDMA_DLENG_REG_ADDR              0x01DCUL
+#define         HW_PKI_SDMA_EXP_POINTERS_REG_ADDR       0x01E0UL
+#define         HW_PKI_SDMA_RES_POINTERS_REG_ADDR       0x01E4UL
+#define         HW_PKI_CLR_REG_ADDR                     0x01E8UL
+#define         HW_PKI_SDMA_BUSY_REG_ADDR                   0x01E8UL
+#define         HW_PKI_SDMA_FIRST_EXP_N_REG_ADDR        0x01ECUL
+#define         HW_PKI_SDMA_MUL_BY1_REG_ADDR            0x01F0UL
+#define         HW_PKI_SDMA_RMUL_SEL_REG_ADDR           0x01F4UL
+#define         HW_DES_KEY_0_REG_ADDR                   0x0208UL
+#define         HW_DES_KEY_1_REG_ADDR                   0x020CUL
+#define         HW_DES_KEY_2_REG_ADDR                   0x0210UL
+#define         HW_DES_KEY_3_REG_ADDR                   0x0214UL
+#define         HW_DES_KEY_4_REG_ADDR                   0x0218UL
+#define         HW_DES_KEY_5_REG_ADDR                   0x021CUL
+#define         HW_DES_CONTROL_0_REG_ADDR               0x0220UL
+#define         HW_DES_CONTROL_1_REG_ADDR               0x0224UL
+#define         HW_DES_IV_0_REG_ADDR                    0x0228UL
+#define         HW_DES_IV_1_REG_ADDR                    0x022CUL
+#define         HW_AES_KEY_0_ADDR_0_REG_ADDR            0x0400UL
+#define         HW_AES_KEY_0_ADDR_1_REG_ADDR            0x0404UL
+#define         HW_AES_KEY_0_ADDR_2_REG_ADDR            0x0408UL
+#define         HW_AES_KEY_0_ADDR_3_REG_ADDR            0x040cUL
+#define         HW_AES_KEY_0_ADDR_4_REG_ADDR            0x0410UL
+#define         HW_AES_KEY_0_ADDR_5_REG_ADDR            0x0414UL
+#define         HW_AES_KEY_0_ADDR_6_REG_ADDR            0x0418UL
+#define         HW_AES_KEY_0_ADDR_7_REG_ADDR            0x041cUL
+#define         HW_AES_KEY_0_REG_ADDR                   0x0400UL
+#define         HW_AES_IV_0_ADDR_0_REG_ADDR             0x0440UL
+#define         HW_AES_IV_0_ADDR_1_REG_ADDR             0x0444UL
+#define         HW_AES_IV_0_ADDR_2_REG_ADDR             0x0448UL
+#define         HW_AES_IV_0_ADDR_3_REG_ADDR             0x044cUL
+#define         HW_AES_IV_0_REG_ADDR                    0x0440UL
+#define         HW_AES_CTR1_ADDR_0_REG_ADDR             0x0460UL
+#define         HW_AES_CTR1_ADDR_1_REG_ADDR             0x0464UL
+#define         HW_AES_CTR1_ADDR_2_REG_ADDR             0x0468UL
+#define         HW_AES_CTR1_ADDR_3_REG_ADDR             0x046cUL
+#define         HW_AES_CTR1_REG_ADDR                    0x0460UL
+#define         HW_AES_SK_REG_ADDR                      0x0478UL
+#define         HW_AES_MAC_OK_REG_ADDR              0x0480UL
+#define         HW_AES_PREV_IV_0_ADDR_0_REG_ADDR        0x0490UL
+#define         HW_AES_PREV_IV_0_ADDR_1_REG_ADDR        0x0494UL
+#define         HW_AES_PREV_IV_0_ADDR_2_REG_ADDR        0x0498UL
+#define         HW_AES_PREV_IV_0_ADDR_3_REG_ADDR        0x049cUL
+#define         HW_AES_PREV_IV_0_REG_ADDR                   0x0490UL
+#define         HW_AES_CONTROL_REG_ADDR                     0x04C0UL
+#define         HW_HASH_H0_REG_ADDR                 0x0640UL
+#define         HW_HASH_H1_REG_ADDR                 0x0644UL
+#define         HW_HASH_H2_REG_ADDR                 0x0648UL
+#define         HW_HASH_H3_REG_ADDR                 0x064CUL
+#define         HW_HASH_H4_REG_ADDR                 0x0650UL
+#define         HW_HASH_H5_REG_ADDR                 0x0654UL
+#define         HW_HASH_H6_REG_ADDR                 0x0658UL
+#define         HW_HASH_H7_REG_ADDR                 0x065CUL
+#define         HW_HASH_H8_REG_ADDR                 0x0660UL
+#define         HW_HASH_H9_REG_ADDR                 0x0664UL
+#define         HW_HASH_H10_REG_ADDR                0x0668UL
+#define         HW_HASH_H11_REG_ADDR                0x066CUL
+#define         HW_HASH_H12_REG_ADDR                0x0670UL
+#define         HW_HASH_H13_REG_ADDR                0x0674UL
+#define         HW_HASH_H14_REG_ADDR                0x0678UL
+#define         HW_HASH_H15_REG_ADDR                0x067CUL
+#define         HW_HASH_CONTROL_REG_ADDR                0x07C0UL
+#define         HW_HASH_PAD_EN_REG_ADDR                 0x07C4UL
+#define         HW_HASH_PAD_CFG_REG_ADDR                0x07C8UL
+#define         HW_HASH_CUR_LEN_0_REG_ADDR      0x07CCUL
+#define         HW_HASH_CUR_LEN_1_REG_ADDR      0x07D0UL
+#define         HW_HASH_CUR_LEN_2_REG_ADDR      0x07D4UL
+#define         HW_HASH_CUR_LEN_3_REG_ADDR      0x07D8UL
+#define         HW_HASH_PARAM_REG_ADDR          0x07DCUL
+#define         HW_HASH_INT_BUSY_REG_ADDR               0x07E0UL
+#define         HW_HASH_SW_RESET_REG_ADDR               0x07E4UL
+#define         HW_HASH_ENDIANESS_REG_ADDR      0x07E8UL
+#define         HW_HASH_DATA_REG_ADDR               0x07ECUL
+#define         HW_DRNG_CONTROL_REG_ADDR                0x0800UL
+#define         HW_DRNG_VALID_REG_ADDR          0x0804UL
+#define         HW_DRNG_DATA_REG_ADDR               0x0808UL
+#define         HW_RND_SRC_EN_REG_ADDR          0x080CUL
+#define         HW_AES_CLK_ENABLE_REG_ADDR      0x0810UL
+#define         HW_DES_CLK_ENABLE_REG_ADDR      0x0814UL
+#define         HW_HASH_CLK_ENABLE_REG_ADDR     0x0818UL
+#define         HW_PKI_CLK_ENABLE_REG_ADDR      0x081CUL
+#define         HW_CLK_STATUS_REG_ADDR          0x0824UL
+#define         HW_CLK_ENABLE_REG_ADDR          0x0828UL
+#define         HW_DRNG_SAMPLE_REG_ADDR                 0x0850UL
+#define         HW_RND_SRC_CTL_REG_ADDR                 0x0858UL
+#define         HW_CRYPTO_CTL_REG_ADDR          0x0900UL
+#define         HW_CRYPTO_STATUS_REG_ADDR               0x090CUL
+#define         HW_CRYPTO_BUSY_REG_ADDR                 0x0910UL
+#define         HW_AES_BUSY_REG_ADDR                0x0914UL
+#define         HW_DES_BUSY_REG_ADDR                0x0918UL
+#define         HW_HASH_BUSY_REG_ADDR               0x091CUL
+#define         HW_CONTENT_REG_ADDR                 0x0924UL
+#define         HW_VERSION_REG_ADDR                 0x0928UL
+#define         HW_CONTEXT_ID_REG_ADDR          0x0930UL
+#define         HW_DIN_BUFFER_REG_ADDR          0x0C00UL
+#define         HW_DIN_MEM_DMA_BUSY_REG_ADDR    0x0c20UL
+#define         HW_SRC_LLI_MEM_ADDR_REG_ADDR    0x0c24UL
+#define         HW_SRC_LLI_WORD0_REG_ADDR               0x0C28UL
+#define         HW_SRC_LLI_WORD1_REG_ADDR               0x0C2CUL
+#define         HW_SRAM_SRC_ADDR_REG_ADDR               0x0c30UL
+#define         HW_DIN_SRAM_BYTES_LEN_REG_ADDR  0x0c34UL
+#define         HW_DIN_SRAM_DMA_BUSY_REG_ADDR   0x0C38UL
+#define         HW_WRITE_ALIGN_REG_ADDR                 0x0C3CUL
+#define         HW_OLD_DATA_REG_ADDR                0x0C48UL
+#define         HW_WRITE_ALIGN_LAST_REG_ADDR    0x0C4CUL
+#define         HW_DOUT_BUFFER_REG_ADDR                 0x0C00UL
+#define         HW_DST_LLI_WORD0_REG_ADDR               0x0D28UL
+#define         HW_DST_LLI_WORD1_REG_ADDR               0x0D2CUL
+#define         HW_DST_LLI_MEM_ADDR_REG_ADDR    0x0D24UL
+#define         HW_DOUT_MEM_DMA_BUSY_REG_ADDR   0x0D20UL
+#define         HW_SRAM_DEST_ADDR_REG_ADDR      0x0D30UL
+#define         HW_DOUT_SRAM_BYTES_LEN_REG_ADDR 0x0D34UL
+#define         HW_DOUT_SRAM_DMA_BUSY_REG_ADDR  0x0D38UL
+#define         HW_READ_ALIGN_REG_ADDR          0x0D3CUL
+#define         HW_READ_LAST_DATA_REG_ADDR      0x0D44UL
+#define         HW_RC4_THRU_CPU_REG_ADDR                0x0D4CUL
+#define         HW_AHB_SINGLE_REG_ADDR          0x0E00UL
+#define         HW_SRAM_DATA_REG_ADDR               0x0F00UL
+#define         HW_SRAM_ADDR_REG_ADDR               0x0F04UL
+#define         HW_SRAM_DATA_READY_REG_ADDR     0x0F08UL
+#define         HW_HOST_IRR_REG_ADDR                     0x0A00UL
+#define         HW_HOST_IMR_REG_ADDR                     0x0A04UL
+#define         HW_HOST_ICR_REG_ADDR                     0x0A08UL
+#define         HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR  0x0A10UL
+#define         HW_HOST_SEP_BUSY_REG_ADDR                    0x0A14UL
+#define         HW_HOST_SEP_LCS_REG_ADDR                     0x0A18UL
+#define         HW_HOST_CC_SW_RST_REG_ADDR               0x0A40UL
+#define         HW_HOST_SEP_SW_RST_REG_ADDR              0x0A44UL
+#define         HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR        0x0A80UL
+#define         HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR        0x0A84UL
+#define         HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR        0x0A88UL
+#define         HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR        0x0A8cUL
+#define         HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR        0x0A90UL
+#define         HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR        0x0A94UL
+#define         HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR    0x0A98UL
+#define         HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR        0x0A9cUL
+#define         HW_HOST_SEP_HOST_GPR0_REG_ADDR   0x0B00UL
+#define         HW_HOST_SEP_HOST_GPR1_REG_ADDR   0x0B04UL
+#define         HW_HOST_SEP_HOST_GPR2_REG_ADDR   0x0B08UL
+#define         HW_HOST_SEP_HOST_GPR3_REG_ADDR       0x0B0CUL
+#define         HW_HOST_HOST_SEP_GPR0_REG_ADDR       0x0B80UL
+#define         HW_HOST_HOST_SEP_GPR1_REG_ADDR       0x0B84UL
+#define         HW_HOST_HOST_SEP_GPR2_REG_ADDR       0x0B88UL
+#define         HW_HOST_HOST_SEP_GPR3_REG_ADDR       0x0B8CUL
+#define         HW_HOST_HOST_ENDIAN_REG_ADDR         0x0B90UL
+#define         HW_HOST_HOST_COMM_CLK_EN_REG_ADDR        0x0B94UL
+#define         HW_CLR_SRAM_BUSY_REG_REG_ADDR        0x0F0CUL
  #define    HW_CC_SRAM_BASE_ADDRESS              0x5800UL

-#endif                         /* ifndef HW_DEFS */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef HW_DEFS */
--
1.6.0.4

--_002_753F67ADE6F5094C9F1DBA00D1BAA8D325518252ACorsmsx501amrc_
Content-Type: text/x-diff;
	name="0001-staging-sep-header-file-updates-for-12-09-software.patch"
Content-Description: 0001-staging-sep-header-file-updates-for-12-09-software.patch
Content-Disposition: attachment;
	filename="0001-staging-sep-header-file-updates-for-12-09-software.patch";
	size=69995; creation-date="Wed, 28 Apr 2010 14:51:17 GMT";
	modification-date="Wed, 28 Apr 2010 14:51:17 GMT"
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