Re: [PATCH] x86: clear XD_DISABLED flag on Intel to regain NX

[H. Peter Anvin]

On 06/17/2010 03:13 PM, Kees Cook wrote:
> This will clear the MSR_IA32_MISC_ENABLE_XD_DISABLE bit so that NX cannot
> be inappropriately controlled by the BIOS on Intel CPUs.  If NX actually
> needs to be disabled, "noexec=off" can be used.
> 
> Signed-off-by: Kees Cook <kees.cook@xxxxxxxxxxxxx>
> ---
>  arch/x86/kernel/head_32.S |   19 +++++++++++++++++++
>  arch/x86/kernel/head_64.S |   18 ++++++++++++++++++
>  arch/x86/mm/setup_nx.c    |    2 +-
>  3 files changed, 38 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
> index 37c3d4b..111e434 100644
> --- a/arch/x86/kernel/head_32.S
> +++ b/arch/x86/kernel/head_32.S
> @@ -309,6 +309,25 @@ ENTRY(startup_32_smp)
>  	subl $0x80000001, %eax
>  	cmpl $(0x8000ffff-0x80000001), %eax
>  	ja 6f
> +
> +	/* Is this "GenuineIntel"? */
> +	movl $0x0, %eax
> +	cpuid
> +	cmpl $0x756e6547, %ebx
> +	jnz 5f
> +	cmpl $0x49656e69, %edx
> +	jnz 5f
> +	cmpl $0x6c65746e, %ecx
> +	jnz 5f
> +
> +	/* Clear MSR_IA32_MISC_ENABLE_XD_DISABLE if set */
> +	movl $MSR_IA32_MISC_ENABLE, %ecx
> +	rdmsr
> +	btrl $2, %edx
> +	jnc 5f
> +	wrmsr
> +
> +5:
>  	mov $0x80000001, %eax
>  	cpuid
>  	/* Execute Disable bit supported? */

Multiple problems with this code.

a) Not all Intel CPUs with extended CPUID levels have
   MSR_IA32_MISC_ENABLE bit 34.  Since we can't take traps here we would
   have to know positively that we aren't going to trip on anything.
b) For 64 bits, this should go into verify_cpu_64.S, and since that is
   32-bit code anyway, it would be best if we could merge the 32- and
   64-bit code into that file; it already simply returns a value
   that could be ignored on 32 bits.

	-hpa
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/