Re: [patch 134/149] x86, paravirt: Add a global synchronization point for pvclock

[H. Peter Anvin]

[Adding H.J. to the Cc: list]

On 07/14/2010 10:57 AM, Jeremy Fitzhardinge wrote:
>>>     
>> I/O ports, for example.
>>   
> 
> Yes, it looks like they should have memory barriers if we want them to
> be ordered with respect to normal writes; afaict "asm volatile" has
> never had strict ordering wrt memory ops.
> 

Noone has talked about strict ordering between volatiles and
(non-volatile) memory ops in general.  I have been talking about
volatile to volatile ordering, and I thought I'd been very clear about that.

H.J., we're having a debate about the actual semantics of "volatile",
especially "asm volatile" in gcc.  In particular, I believe that
volatile operations should not be possible to reorder with regards to
each other, and the kernel depends on that fact.

	-hpa

P.S: gcc 4.4 seems to handle "const volatile" incorrectly, probably by
applying CSE to those values.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/