On Wed, Jul 28, 2010 at 07:34:11AM -0400, Avi Kivity wrote:On 07/28/2010 02:25 PM, Roedel, Joerg wrote:Instruction intercepts take precedence over exception intercepts. So ifOn Wed, Jul 28, 2010 at 06:28:06AM -0400, Avi Kivity wrote:L1 thinks the memory is RAM, so it maps it directly and forgets aboutWe have a slightly different problem, if the nested guest manages to getI wonder how this could happen. Shouldn't the shadow paging code take
an instruction to be emulated by the host (if the guest assigned it the
cirrus framebuffer, for example, so from L1's point of view it is RAM,
but from L0's point of view it is emulated), then we miss the
intercept. L2 could take over L1 this way.
care of this?
it. L0 knows it isn't, so it leaves it unmapped and emulates any
instruction which accesses it. The emulator needs to check whether the
instruction is intercepted or not.
the L2 executes an instruction which the L1 hypervisor wants to
intercept we get this instruction intercept on the host side and
re-inject it.
To my understanding the fault-intercept which causes the emulator to run
can only happen if the instruction causing the fault isn't intercepted
itself.
Note, I think if the instruction operand is in mmio, we're safe, sinceRight. But if the guest executes code which is on mmio we are doomed
the intercept has higher priority than memory access. But if the
instruction itself is on mmio, or if we entered the emulator through smp
trickery, then the emulator will execute the instruction in nested guest
context.
anyway because our instruction emulator does not emulate the whole x86
instruction set, right?