Re: PCI-E Link training bug

[Jesse Barnes]

On Tue, 03 Aug 2010 08:30:41 -0400
Valdis.Kletnieks@xxxxxx wrote:

> On Tue, 03 Aug 2010 00:36:35 -1000, Jeff Roberson said:
> 
> > At least one intel chipset will occasionally negotiate a 4x link for an 8x 
> > device in an 8x port.  It is a known errata in the 5400 mch.  
> 
> Can this get wrapped in some sort of 'if (chipset == MCH5400)'?  There's no
> sense in adding an entire second of delay going around this loop 4 times when
> it's a valid config on a non-5400 chipset.

Yeah, it would be good to limit it to affected chipsets.  Also, please
post it to linux-pci@xxxxxxxxxxxxxxx as well, and cc me, and we'll get
the fix in quickly.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center
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