Re: [tip:irq/core] x86: Sanitize apb timer interrupt handling

[Thomas Gleixner]

On Tue, 12 Oct 2010, Jacob Pan wrote:

> Thomas Gleixner Tue, 12 Oct 2010 23:28:19 +0200 (CEST)
> >On Tue, 12 Oct 2010, Jacob Pan wrote:
> >
> >> 
> >> >x86: Sanitize apb timer interrupt handling
> >> >
> >> >Disable the interrupt in CPU_DEAD where it belongs.
> >> My main concern is the performance cost. The power management code for
> >> Moorestown system make use of the cpu hotplug code (disable_nonboot_cpus)
> >> but much more frequently. The system low power states are call S0 idle
> >> state (s0ix).
> >> 
> >> Leaving the irq enabled at the chip and desc level between S0ix states
> >> might give some performance benefit. That was my original thought.
> >> Will it cause problems?
> >
> >Errm. I merily moved it to the place where it should be. You do the
> >disable/enable dance already today.
> >
> I think I only do disable/enable at the timer HW level today during cpu hp
> notification, not calling disable_irq(). Am i missing something?

apbt_setup_irq()
{
 ...
 
--->	disable_irq(adev->irq);
	desc->status |= IRQ_MOVE_PCNTXT;
	irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
	/* APB timer irqs are set up as mp_irqs, timer is edge triggerred */
	set_irq_chip_and_handler_name(adev->irq, chip, handle_edge_irq, "edge");
--->	enable_irq(adev->irq);
	if (system_state == SYSTEM_BOOTING)
 ...
}

So that's a disable/enable pair on every cpu hotplug, right ?

Now I moved the disable to CPU_DEAD where it belongs and the enable
stayed at the same place.

Thanks,

	tglx
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