Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES andPERF_COUNT_HW_CACHE_MISSES for AMD

From: Stephane Eranian
Date: Mon Nov 01 2010 - 21:55:55 EST


Hi,



On Mon, Nov 1, 2010 at 3:11 PM, Robert SchÃne
<robert.schoene@xxxxxxxxxxxxx> wrote:
>
> The current arch/x86/kernel/cpu/perf_event_amd.c file lists
> L1-Instruction-Cache Misses and Accesses as PERF_COUNT_HW_CACHE_MISSES
> resp. PERF_COUNT_HW_CACHE_REFERENCES.
>
I always thought PERF_COUNT_HW_CACHE_* was about data cache misses.
But given that there is no clear definitions for those events, it
creates confusion.

If you change the meaning of HW_CACHE_MISSES, then seems to me, you need
to change the mapping in the perf tool, because now it includes both data+code.


> This fix uses L2C-Misses and Accesses instead. (Real LLC-events would be
> better, but there are some restrictions for Northbridge Events on AMD).
>
And those constraints are handled correctly by the kernel.

The constraint is such that you cannot have more than 4 instances of
Northbridge events active at the same time per core. If you do, then one
of them will starve (if issued from different cores).


> --- a/arch/x86/kernel/cpu/perf_event_amd.c
> +++ b/arch/x86/kernel/cpu/perf_event_amd.c
> @@ -100,8 +100,8 @@ static const u64 amd_perfmon_event_map[] =
> Â{
> Â [PERF_COUNT_HW_CPU_CYCLES] Â Â Â Â Â = 0x0076,
> Â [PERF_COUNT_HW_INSTRUCTIONS] Â Â Â Â = 0x00c0,
> - Â[PERF_COUNT_HW_CACHE_REFERENCES] Â Â = 0x0080,
> - Â[PERF_COUNT_HW_CACHE_MISSES] Â Â Â Â = 0x0081,
> + Â[PERF_COUNT_HW_CACHE_REFERENCES] Â Â = 0x037D,
> + Â[PERF_COUNT_HW_CACHE_MISSES] Â Â Â Â = 0x037E,
> Â [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] Â= 0x00c2,
> Â [PERF_COUNT_HW_BRANCH_MISSES] Â Â Â Â Â Â Â Â= 0x00c3,
> Â};
>
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