Re: [V2 PATCH 0/6] x86, NMI: give NMI handler a face-lift

[Cyrill Gorcunov]

On Thu, Nov 18, 2010 at 02:32:47PM -0500, Don Zickus wrote:
> On Thu, Nov 18, 2010 at 02:17:12PM +0100, Peter Zijlstra wrote:
> > On Thu, 2010-11-18 at 06:47 -0600, Jason Wessel wrote:
> > > More specifically
> > > when another subsystem injects an NMI event the perf NMI code returns
> > > NOTIFY_STOP. 
> > 
> > Not unconditionally, right? We only do so when the previous NMI was from
> > the PMU and nobody claimed this one (NOTIFY_STOP from DIE_NMIUNKNOWN).
> > 
> > Or are you hitting the other one, where !handled but pmu_nmi.handled >
> > 1 ?
> 
> I think the problem with the virt stuff is that it emulates 0 to the
> rdmsrl calls.  All platforms except perf_events_intel.c rely on checking
> the high bit of the counter register to not be zero, otherwise the code
> thinks it crossed zero and triggered an PMI.
> 
> The intel code is a litte smarter and relies on the interrupt logic and
> thus doesn't have this problem (to clarify only core2 and later use this,
> p4 and p6 use the old methods).
> 
> So the problem is when the nmi watchdog is enabled, the perf event is
> 'active' and thus tries to read the counter value.  Because it is always
> zero, perf just assumes the counter overflowed and the NMI is his.
> 
> Not sure how to fix it yet, other than include the logic that detects we
> are on a guest and disable perf??
> 
> On a side note I think I have a fix for the p4 problem but will probably
> need Cyril to look at it.  Basically in, p4_pmu_clear_cccr_ovf() it is
> using the high part of the cccr register to determine if the counter
> overflowed, when it probably wants to use the low bits of the cccr
> register and high bits of the event_base.
> 
> Cheers,
> Don
>

good observation Don! One of the problem is that some overflow may happen
without setting 'overflow' control bit but have to check the high bits.
not sure I follow the kvm part, you mean rdmsrl returns 0?
 
  Cyrill
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