Re: [RFC PATCH 2/3 v2] perf: Implement Nehalem uncore pmu

[Stephane Eranian]

On Fri, Nov 26, 2010 at 6:15 AM, Lin Ming <lin@xxxxxxx> wrote:
> On Tue, Nov 23, 2010 at 6:17 PM, Stephane Eranian <eranian@xxxxxxxxxx> wrote:
>> Lin,
>>
>> On Sun, Nov 21, 2010 at 1:01 PM, Lin Ming <ming.m.lin@xxxxxxxxx> wrote:
>>> +static void uncore_pmu_enable_all(void)
>>> +{
>>> + Â Â Â u64 ctrl;
>>> +
>>> + Â Â Â /*
>>> + Â Â Â Â* (0xFULL << 48): 1 of the 4 cores can receive NMI each time
>>> + Â Â Â Â* but we don't know which core will receive the NMI when overflow happens
>>> + Â Â Â Â*/
>>
>> That does not sound right. If you set bit 48-51 to 1, then all 4 cores
>> will receive EVERY
>> interrupt, i.e., it's a broadcast. That seems to contradict your
>> comment: 1 of the 4. Unless
>> you meant, they all get the interrupt and one will handle it, the
>> other will find nothing to
>> process. But I don't see the atomic op that would make this true in
>> uncore_handle_irq().
>
> Stephane,
>
> The interrupt model is strange, it behaves differently when HT on/off.
>
> If HT is off, all 4 cores will receive every interrupt, i.e., it's a broadcast.
>
That's if yo set the mask to 0xf, right?

In the perf_event model, given that any one of the 4 cores can be used
to program uncore events, you have no choice but to broadcast to all
4 cores. Each has to demultiplex and figure out which of its counters
have overflowed.

> If HT is on, only 1 of the 4 cores will receive the interrupt(both
> Threads in that core receive the interrupt),
> and it can't be determined which core will receive the interrupt.
>
> Did you ever observe this?
>
No because I never set more than one bit in the mask.

> I tried to set the mask 0xff when HT is on, but kernel panics, because
> the reserve bits are set.

Let me check on this. It would seem to imply that in HT mode, both threads
necessarily receive the interrupts.

Was that on Nehalem or Westmere?
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