Re: [PATCH 2/7] perf-events: Add support for supplementary event registers v4

[Andi Kleen]

On Thu, Jan 13, 2011 at 06:31:03PM +0100, Stephane Eranian wrote:
> Hi,
> 
> I'd like to suggest that the OFFCORE_RESPONSE extra MSR encoding
> be put into a dedicated field in the perf_event_attr instead of in the upper
> 32-bits of attr->config.


That's what the first revision of the patch did.
I can change it back to that.

Small drawback was that it needs more changes to the user tool,
but the patch was not very big.

> 
> There may not be enough space to encode for future processors.
> 
> In fact, given that the Sandy Bridge PMU spec is now available, we
> have a first example of this (see Vol3b figure 30.29). OFFCORE_RESPONSE
> needs 38 bits. So, instead of having NHM/WSM use attr->config and SNB


That makes sense.

> use another field, I think it would make sense to have that in a new u64 field
> for all processors. Despite the fact that OFFCORE_RESPONSE remains
> a model-specific feature, I think it would help user tools and libraries if we
> were to use a dedicated field.


-Andi
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