[PATCH 0/4] x86, amd: family 0x15 L3 cache features

From: Hans Rosenfeld
Date: Mon Jan 24 2011 - 10:06:00 EST

This patch set enables L3 cache index disable and adds support for L3
cache partitioning on AMD family 0x15 CPUs.

This stuff applies against tip/master 3ff6dcac735704824c1dff64dc6863c390d364cc.

Andreas Herrmann (1):
x86, amd: Normalize compute unit IDs on multi-node processors

Hans Rosenfeld (3):
x86, amd: Enable L3 cache index disable on family 0x15
x86, amd: Extend AMD northbridge caching code to support "Link
Control" devices
x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs

arch/x86/include/asm/amd_nb.h | 4 ++
arch/x86/kernel/amd_nb.c | 69 ++++++++++++++++++++++++++++++-
arch/x86/kernel/cpu/amd.c | 8 +++-
arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++-----
arch/x86/kernel/smpboot.c | 1 +
include/linux/pci_ids.h | 1 +
6 files changed, 140 insertions(+), 16 deletions(-)

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