Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support forre-enabling l2x0

[Russell King - ARM Linux]

On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar wrote:
> GIC save/restore on OMAP follows different strategy. There is a
> Predefined layout to save content and restore is done atomically
> by boot ROM code.
> L2 cache also same case. Only AUXCTRL needs to be programmed on
> wakeup from low power mode and that too with secure call. Rest
> of the registers are managed by boot ROM code.
> 
> TWD is already managed through framework. Othe CPU low power
> sequence is very small and OMAP has restrictions on the last
> core to go down and first to wakeup.
> 
> So at least I don't see any use of common notifiers for GIC
> and L2 will help OMAP lower power code.

What this means is that we're going to end up littering things like GIC
and other stuff with lots of individual SoC specific code to save state
into individual SoC specific structures.  This is not sane, and we're
not going to corrupt generic code with SoC specific code.
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