Re: [PATCH v4] net: add Faraday FTMAC100 10/100 Ethernet driver
From: Po-Yu Chuang
Date: Thu Feb 24 2011 - 03:08:15 EST
On Thu, Feb 24, 2011 at 3:51 PM, David Miller <davem@xxxxxxxxxxxxx> wrote:
> From: Po-Yu Chuang <ratbert.chuang@xxxxxxxxx>
> Date: Thu, 24 Feb 2011 15:27:55 +0800
>> I guess the problem is because a HW restriction that the rx buffer must be
>> 64 bits aligned. Since I cannot make rx buffer starts at offset 2 bytes, the
>> IP header, TCP header and data are not 4 bytes aligned. The performance
>> drops drastically.
> I cannot believe that after 20 years of commodity ethernet networking
> chips were first designed, people are still designing hardware that
> doesn't do this right.
Well, this restriction was removed in the later IPs of our company. :-p
> Just emit garbage bytes into the sub-word alignment padding if the chip
> wants to word align it's DMA writes.
Not sure what do you mean. The problem is that HW does not accept a
base address of RX buffer which is not 8 bytes aligned.
> Even the 15 year old Dec Tulip chips do this properly.
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