Re: [PATCH v2 -tip] perf: x86, add SandyBridge support
From: Stephane Eranian
Date: Mon Feb 28 2011 - 09:13:23 EST
Also for offcore_reponse_*, the fact that they are marked as PMC3 only is just
a convenience for scheduling. Given both events need an extra MSR, it makes
scheduling easier if you consider offcore_reponse_0 to work only on one counter.
That guarantees there won't be conflict on that extra MSR. The downside, is that
you cannot measure the event twice if you only want to vary the counter filters
(not the extra MSR), e.g., measure one instance at user level and the other at
On SNB, the extra MSRs are not shared by HT threads anymore (Table B-9).
That means that in the offcore patch, the extra_config logic is needed but not
the mutual exclusion between HT threads.
On Mon, Feb 28, 2011 at 3:02 PM, Lin Ming <ming.m.lin@xxxxxxxxx> wrote:
> On Mon, 2011-02-28 at 17:08 +0800, Ingo Molnar wrote:
>> * Lin Ming <ming.m.lin@xxxxxxxxx> wrote:
>> > > In other words, bit 0-3 of the umask cannot be zero.
>> > I got the umask from "Table 30-20. PEBS Performance Events for Intel
>> > microarchitecture code name Sandy Bridge".
>> > But from "Table A-2. Non-Architectural Performance Events In the Processor Core
>> > for Intel Core Processor 2xxx Series", the combinations are needed as you show
>> > above.
>> > Which one is correct?
>> Since you have access to the hardware, could you please test and see it in practice
>> which one is correct?
> Stephane is right, need the combination.
> Sorry that I may made mistake when I tested 0xd0 pebs events.
> Re-test all PEBS events, now only below 2 events need more support to
> PEBS_EVENT_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
> PEBS_EVENT_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORE*/
>> Â Â Â Ingo
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