Re: [PATCH 4/4] msm: scm: Get cacheline size from CTR
From: Stephen Boyd
Date: Mon Feb 28 2011 - 23:21:08 EST
On 02/24/2011 11:56 AM, Thomas Gleixner wrote:
> On Thu, 24 Feb 2011, Stephen Boyd wrote:
>> I definitely don't want to do it for every loop. I'm fine with getting
>> it every scm_call() invocation though.
>> For now, I'll pull the end and cacheline_size variables out of the
>> do-while loop.
> Why not do it correct right away and retrieve it in an __init
That would require an early_initcall, so hopefully that is fine.
I wonder why the generic arm v7 cache operations don't do the same thing
and store the dcache line size somewhere. Every dma operation is
essentially calling dcache_line_size(). Perhaps some generic arm code
should be determining the dcache line size really early on and storing
it in the proc_info_list? Then both the dma code and scm code could
query the processor for the dcache line size with something like
Sent by an employee of the Qualcomm Innovation Center, Inc.
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