Re: [RFC][PATCH 2/6] mm: Change flush_tlb_range() to take anmm_struct

[David Miller]

From: Peter Zijlstra <a.p.zijlstra@xxxxxxxxx>
Date: Wed, 02 Mar 2011 22:40:27 +0100

> On Wed, 2011-03-02 at 11:19 -0800, Linus Torvalds wrote:
>> On Wed, Mar 2, 2011 at 9:59 AM, Peter Zijlstra <a.p.zijlstra@xxxxxxxxx> wrote:
>> > In order to be able to properly support architecture that want/need to
>> > support TLB range invalidation, we need to change the
>> > flush_tlb_range() argument from a vm_area_struct to an mm_struct
>> > because the range might very well extend past one VMA, or not have a
>> > VMA at all.
>> 
>> I really don't think this is right. The whole "drop the icache
>> information" thing is a total anti-optimization, since for some
>> architectures, the icache flush is the _big_ deal. 
> 
> Right, so Tile has the I-cache flush from flush_tlb_range(), I'm not
> sure if that's the right thing to do, Documentation/cachetlb.txt seems
> to suggest doing it from update_mmu_cache() like things.

Sparc32 chips that require a valid TLB entry for I-cache flushes do
the flush from flush_cache_range() and similar.

Sparc64 does not have the "present TLB entry" requirement (since I-cache
is physical), and we handle it in update_mmu_cache() but only as an
optimization.  This scheme works in concert with flush_dcache_page().

Either scheme is valid, the former is best when flushing is based upon
virtual addresses.

But I'll be the first to admit that the interfaces we have for doing
this stuff is basically nothing more than a set of hooks, with
assurances that the hooks will be called in specific situations.  Like
anything else, it's evolved over time based upon architectural needs.

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