Re: [RFC][PATCH 2/6] mm: Change flush_tlb_range() to take an mm_struct

[Chris Metcalf]

On 3/3/2011 1:45 PM, David Miller wrote:
>> I'm finding it hard to understand how the Sparc code handles icache
>> coherence.  It seems that the Spitfire MMU is the interesting one, but the
>> hard case seems to be when a process migrates around to various cores
>> during execution (thus leaving incoherent icache lines everywhere), and the
>> page is then freed and re-used for different executable code.  I'd think
>> that there would have to be xcall IPIs to flush all the cpus' icaches, or
>> to flush every core in the cpu_vm_mask plus do something at context switch,
>> but I don't see any of that.  No doubt I'm missing something :-)
> flush_dcache_page() remembers the cpu that wrote to the page (in the
> page flags), and cross-calls to that specific cpu.
>
> It is only that cpu which must flush his I-cache, since all other cpus
> saw the write on the bus and updated their I-cache lines as a result.
>
> See, in the sparc64 case, the incoherency issue is purely local to the
> store.  The problem case is specifically the local I-cache not seeing
> local writes, everything else is fine.  CPU I-caches see writes done
> by other cpus, just not those done by the local cpu.

Thanks, that makes sense.  Our architecture has no bus to snoop, so we
couldn't take advantage of that approach.

-- 
Chris Metcalf, Tilera Corp.
http://www.tilera.com

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