Re: [PATCH v2] x86/mrst: correct pin to irq mapping

[jacob pan]

On Sun, 10 Apr 2011 08:01:54 +0200
Ingo Molnar <mingo@xxxxxxx> wrote:

> 
> * Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx> wrote:
> 
> > As a result, apbt timer and RTC interrupts on Moorestown are within
> > legacy IRQ range.
> > 
> > sh-3.2# cat /proc/interrupts
> >            CPU0       CPU1
> >   0:      11249          0   IO-APIC-edge      apbt0
> >   1:          0      12271   IO-APIC-edge      apbt1
> >   8:        887          0   IO-APIC-fasteoi   dw_spi
> >  13:          0          0   IO-APIC-fasteoi   INTEL_MID_DMAC2
> >  14:          0          0   IO-APIC-fasteoi   rtc0
> 
> Is there a 'before the patch' /proc/interrupts output as well?
> Supposedly it's different and seeing that different output is *way*
> more descriptive to the casual commit log reader than a textual
> explanation only.
> 
If v1 patch is used, /proc/interrupts look like below on Moorestown.
Notice that apbt1 interrupts is moved to gsi_top + 1 = 39.

bash-3.2# cat /proc/interrupts 
           CPU0       CPU1       
  0:     793303          0   IO-APIC-edge      apbt0
  8:      84124          0   IO-APIC-fasteoi   dw_spi
 13:          0          0   IO-APIC-fasteoi   INTEL_MID_DMAC2
 15:    1851630          0   IO-APIC-fasteoi   mrstouch
 27:         83          0   IO-APIC-fasteoi   mmc0l_scu_ipc
 28:          0          0   IO-APIC-fasteoi   mmc1
 30:          0          0   IO-APIC-fasteoi   INTEL_MID_DMAC1
 33:         23          0   IO-APIC-fasteoi   ehci_hcd:usb1
 34:         52          0   IO-APIC-fasteoi   mmc2
 39:          0     812273   IO-APIC-edge      apbt1



> Also, i guess this would be .40 material, right?
Without the patch, kernel will crash during boot on Moorestown since
the secondary CPU clockevent (apbt1) will fail to request irq#1, which
does not have ioapic chip in its irq_desc[] entry. So, I would think
this is an urgent bug fix for 39.


-- 
Thanks

Jacob
(from Linux laptop)
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