[tip:perf/urgent] perf: Support Xeon E7's via the Westmere PMU driver

[tip-bot for Andi Kleen]

Commit-ID:  b2508e828d71baacd9a743dd48dcbf85d96affdd
Gitweb:     http://git.kernel.org/tip/b2508e828d71baacd9a743dd48dcbf85d96affdd
Author:     Andi Kleen <ak@xxxxxxxxxxxxxxx>
AuthorDate: Thu, 21 Apr 2011 16:48:35 -0700
Committer:  Ingo Molnar <mingo@xxxxxxx>
CommitDate: Fri, 22 Apr 2011 08:27:29 +0200

perf: Support Xeon E7's via the Westmere PMU driver

There's a new model number public, 47, for Xeon E7 (aka Westmere EX).

Signed-off-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
Cc: a.p.zijlstra@xxxxxxxxx
Link: http://lkml.kernel.org/r/1303429715-10202-1-git-send-email-andi@xxxxxxxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxx>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 8fc2b2c..586cced 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1425,6 +1425,7 @@ static __init int intel_pmu_init(void)
 
 	case 37: /* 32 nm nehalem, "Clarkdale" */
 	case 44: /* 32 nm nehalem, "Gulftown" */
+	case 47: /* 32 nm Xeon E7 */
 		memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
--
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