Re: [generalized cache events] Re: [PATCH 1/1] perf tools: Addmissing user space support for config1/config2

[Ingo Molnar]

* Stephane Eranian <eranian@xxxxxxxxxx> wrote:

> On Sat, Apr 23, 2011 at 9:50 AM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > On Fri, 2011-04-22 at 17:03 -0700, Andi Kleen wrote:
> >> > > Yes, and note that with instructions events we even have skid-less PEBS
> >> > > profiling so seeing the precise .
> >> >                                   - location of instructions is possible.
> >>
> >> It was better when it was eaten. PEBS does not actually eliminated
> >> skid unfortunately. The interrupt still occurs later, so the
> >> instruction location is off.
> >>
> >> PEBS merely gives you more information.
> >
> > You're so skilled at not actually saying anything useful. Are you
> > perchance referring to the fact that the IP reported in the PEBS data is
> > exactly _one_ instruction off? Something that is demonstrated to be
> > fixable?
> >
> > Or are you defining skid differently and not telling us your definition?
> >
> 
> PEBS is guaranteed to return an IP that is just after AN instruction that 
> caused the event. However, that instruction is NOT the one at the end of your 
> period. Let's take an example with INST_RETIRED, period=100000. Then, the IP 
> you get is NOT after the 100,000th retired instruction. It's an instruction 
> that is N cycles after that one. There is internal skid due to the way PEBS 
> is implemented.

You are really misapplying the common-sense definition of 'skid'.

Skid refers to the instruction causing a profiler hit being mis-identified. 
Google 'x86 pmu skid' and read the third entry: your own prior posting ;-)

What you are referring to here is not really classic skid but a small, mostly 
constant skew in the period length with some very small amount of variability. 
It's thus mostly immaterial - at most a second or third order effect with 
typical frequencies of sampling.

Thanks,

	Ingo
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