Re: [PATCH 3/4] perf, nmi: Move LVT un-masking into irq handlers

From: Don Zickus
Date: Mon Apr 25 2011 - 09:40:37 EST


On Fri, Apr 22, 2011 at 10:26:36AM +0200, Ingo Molnar wrote:
>
> * Don Zickus <dzickus@xxxxxxxxxx> wrote:
>
> > --- a/arch/x86/kernel/cpu/perf_event.c
> > +++ b/arch/x86/kernel/cpu/perf_event.c
> > @@ -1284,6 +1284,9 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
> >
> > cpuc = &__get_cpu_var(cpu_hw_events);
> >
> > + /* chipsets have their own quirks when to unmask */
> > + apic_write(APIC_LVTPC, APIC_DM_NMI);
> > +
>
> What sense does this comment make in this place?
>
> Yes, chipsets have their own quirks - but the generic handler is not one of
> them. So a more appropriate comment would be to point out why we want to unmask
> there - before PMU handling or after it, etc.

Yup. I rework that.

>
> Like the P4 quirk is documented a bit better:
>
> > + /*
> > + * P4 quirks:
> > + * - An overflown perfctr will assert its interrupt
> > + * until the OVF flag in its CCCR is cleared.
> > + * - LVTPC is masked on interrupt and must be
> > + * unmasked by the LVTPC handler.
> > + */
> > + apic_write(APIC_LVTPC, APIC_DM_NMI);
>
> (btw., there's whitespace damage above as well.)
>
> Furthermore, the P4 comment should *explain* the quirk coherently, not just
> list random facts. What happens, why, where, and why do we unmask the LVTPC in
> that spot.

Yeah, I copied that from the old watchdog code. I'll revise that too and
repost.

Cheers,
Don
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