Re: [PATCH 3/7] [RFC] add support for BlueGene/P FPU
From: Eric Van Hensbergen
Date: Thu May 19 2011 - 17:55:19 EST
Damnit Mikey, just after I hit send on [V2].....
On Thu, May 19, 2011 at 4:36 PM, Michael Neuling <mikey@xxxxxxxxxxx> wrote:
> In message <BANLkTimKhApFW8G1-pG0u_9Kv2YB0R1O0w@xxxxxxxxxxxxxx> you wrote:
>> On Thu, May 19, 2011 at 12:58 AM, Michael Neuling <mikey@xxxxxxxxxxx> wrote=
>> > Eric,
>> >> This patch adds save/restore register support for the BlueGene/P
>> >> double hummer FPU.
>> > What does this mean? =A0Needs more details here.
okay, I've changed it a bit in [V2], if you want more I can do my best.
>> "Each of the two FPU units contains 32 64-bit floating point registers
>> for a total of 64 FP registers per processor." which would seem to
>> point to the kittyhawk version - but they have a second SAVE_32SFPRS
>> for the second hummer. What wasn't clear to me with this version of
>> the code was whether or not they were doing something clever like
>> saving the pair of the 64-bit FPU registers in a single 128-bit slot
>> (seems plausible).
> Ok, sounds like there is 32*8*2 bytes of data, rather than the normal
> 32*8 bytes for FP only (ignoring VSX). If this is the case, then you'll
> need make 'fpr' in the thread struct bigger which you can do by setting
> TS_FPRWIDTH = 2 like we do for VSX.
Okay, I'll incorporate that into [V3].
> If there is some instruction that saves and restores two of these at a
> time (which LFPDX/STFPDX might I guess), then we can use that, otherwise
> we'll have to do 64 saves/restores. Double load/stores will be faster
> I'm guessing though.
I assume that's true.
> If two at a time, do we need to increase the index in pairs?
I don't believe so.
>> If this is not the way to go, I can certainly
>> switch the kittyhawk version of the patch with the *, the extra
>> SAVE32SFPR and the extra double hummer specific storage space in the
> I'd be tempted to keep it in the 'fpr' part of the struct so you can
> then access it with ptrace/signals/core dumps.
>> If it would help I can post an alternate version of the patch for
>> discussion with the kittyhawk version.
Kittyhawk version can be seen here:
> The most useful thing would be to see the instruction definition for
>> >> =A0/*
>> >> diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms=
>> > Kconfig
>> >> index f485fc5f..24a515e 100644
>> >> --- a/arch/powerpc/platforms/44x/Kconfig
>> >> +++ b/arch/powerpc/platforms/44x/Kconfig
>> >> @@ -169,6 +169,15 @@ config YOSEMITE
>> >> =A0 =A0 =A0 help
>> >> =A0 =A0 =A0 =A0 This option enables support for the AMCC PPC440EP evalua=
>> tion board.
>> >> +config =A0 =A0 =A0 BGP
>> > Does this FPU feature have a specific name like double hammer? =A0I'd
>> > rather have the BGP defconfig depend on PPC_FPU_DOUBLE_HUMMER, or
>> > something like that...
>> >> + =A0 =A0 bool "Blue Gene/P"
>> >> + =A0 =A0 depends on 44x
>> >> + =A0 =A0 default n
>> >> + =A0 =A0 select PPC_FPU
>> >> + =A0 =A0 select PPC_DOUBLE_FPU
>> > ... in fact, it seem you are doing something like these here but you
>> > don't use PPC_DOUBLE_FPU anywhere?
>> A fair point. I'm fine with calling it DOUBLE_HUMMER, but I wasn't sure if
>> that was "too internal" of a name for the kernel. Let me know and
>> I'll fix it up.
> What I'm mostly concerned about is disassociating it with a particular
> If it has an external name, then all the better.
Since it isn't available on other chips, shoudl it just be PPC_BGP_FPU
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