Re: PCI BAR1 Unassigned

From: Jan Zwiegers
Date: Fri May 20 2011 - 03:42:22 EST

On 2011-05-19 10:50 PM, Xianghua Xiao wrote:
On Thu, May 19, 2011 at 3:27 PM, Jan Zwiegers<jan@xxxxxxxxxxxxxxxxxxxx> wrote:
On 2011-05-19 08:50 PM, Bjorn Helgaas wrote:

On Thu, May 19, 2011 at 10:28 AM, Jan Zwiegers<jan@xxxxxxxxxxxxxxxxxxxx>

I have the problem below where my PCI card's second BAR does not get
What can be the cause of this problem?
The last kernel I tested on which worked OK was 2.6.27.
My current problematic kernel 2.6.35.

05:01.0 Unassigned class [ff00]: Eagle Technology PCI-703 Analog I/O Card
(rev 5c)
Flags: bus master, slow devsel, latency 32, IRQ 22
Memory at 93b00000 (type 3, prefetchable) [size=2K]
Memory at<unassigned> (type 3, prefetchable)
Capabilities: [80] #00 [0600]
Kernel modules: pci703drv

Could be resource exhaustion or, more likely, we ran out because we
now assign resource to things that don't need them, leaving none for
things that *do* need them. This sounds like a regression, so we
should open a bugzilla for it and attach dmesg logs from 2.6.27 and

Does this problem keep the driver from working? (Sometimes drivers
don't actually use all the BARs a device supports.)


I'm the maintainer of the driver and was involved in the development of the
board as well in 2003. The board uses two BARS and the second BAR is the
most important. The board worked fine since the 2.4 days and only recently
became problematic. I suspect it works on even later kernels than 27, maybe

My knowledge is too little to actually determine if the problem is because
the FPGA based PCI interface is not within spec or something that changed in
the kernel, because of the post .30 releases becoming more strict to PCI
specification, i.e. BIOS / Kernel interaction.

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What's the size for BAR1? one reason is that no more space to
align/allocate BAR1.

If the board stays the same then your FPGA might be the cause, I have
seen similar issues and they ended up in FPGA implementation.

I have submitted the difference in iomem, lspci and dmesg of 2.6.27 & 2.6.35 kernels from the same machine. The BAR size is 2K. As above BAR0 is at 93b0000 and BAR1 should be at 93b00800.

The board has been fine since 2003, so I'm confident the FPGA is within spec.

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