Re: [PATCH 3/3] perf_events: add Intel Sandy Bridgeoffcore_response low-level support (v3)

From: Peter Zijlstra
Date: Mon May 23 2011 - 12:22:06 EST

On Mon, 2011-05-23 at 18:12 +0200, Stephane Eranian wrote:
> This patch adds Intel Sandy Bridge offcore_response support by
> providing the low-level constraint table for those events.
> On Sandy Bridge, there are two offcore_response events. Each uses
> its own dedictated extra register. But those registers are NOT shared
> between sibling CPUs when HT is on unlike Nehalem/Westmere. They are
> always private to each CPU. But they still need to be controlled within
> an event group. All events within an event group must use the same
> value for the extra MSR. That's not controlled by the second patch in
> this series.
> Furthermore on Sandy Bridge, the offcore_response events have NO
> counter constraints contrary to what the official documentation
> indicates, so drop the events from the contraint table.

You sending this suggests you actually have a SNB machine, do you also
happen to know how to use those SNB RSP MSRs? Lin Ming and I were
wondering how to fill out the extra-regs for

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at
Please read the FAQ at