Re: [RFC -tip] perf, x86: Add PERF_COUNT_HW_NMI_WATCHDOG event v2

[Stephane Eranian]

On Thu, Jun 23, 2011 at 8:48 AM, Cyrill Gorcunov <gorcunov@xxxxxxxxx> wrote:
> On Wed, Jun 22, 2011 at 01:21:34PM +0400, Cyrill Gorcunov wrote:
> ...
>> Note that I've not tested it but rather need approval/rejecting
>> on idea in general.
>
> The final version is below. Stephane, note that it's almost the
> same idea as you proposed except it uses explicit namings to
> mark out that watchdog cycles are special.
>
This looks okay.

The only alternative I see (This is wha I had in mind at the
beginning) that would
not require this new hidden generic event would be to have watchdog.c invoke an
arch-specific callback to fill out the attr.type, attr->config fields directly:

static int watchdog_nmi_enable(int cpu)
{
        struct perf_event_attr *wd_attr;
        struct perf_event *event = per_cpu(watchdog_ev, cpu);

        /* is it already setup and enabled? */
        if (event && event->state > PERF_EVENT_STATE_OFF)
                goto out;

        /* it is setup but not enabled */
        if (event != NULL)
                goto out_enable;

        /* Try to register using hardware perf events */
        wd_attr = &wd_hw_attr;
        wd_attr->sample_period = hw_nmi_get_sample_period(watchdog_thresh);

-->    hw_nmi_get_event(wd_attr);

        event = perf_event_create_kernel_counter(wd_attr, cpu, NULL,
watchdog_overflow_callback);
        ...
}

wd_attr would still be hardcoded with CPU_CYCLES, but could be overriden.
A default and empty hw_nmi_get_event() would be defined as __weak in watchdog.c.

Then for x86(), it would do what you have in your patch:

hw_nmi_get_event(struct perf_event *event)
{
       if (x86_pmu.hw_watchdog_config)
               x86_pmu.hw_watchdog_config(event);
}

For P4, hw_watchdog_config(), would be defined as in your patch:

+static void p4_hw_watchdog_config(struct perf_event *event)
+{
+       /*
+        * Watchdog ticks are special on Netburst, we use
+        * that named "non-sleeping" ticks as recommended
+        * by Intel SDM Vol3b.
+        */
+       event->attr.type        = PERF_TYPE_RAW;
+       event->attr.config      =
+
p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_EXECUTION_EVENT)
 |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
NBOGUS0)            |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
NBOGUS1)            |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
NBOGUS2)            |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
NBOGUS3)            |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
BOGUS0)             |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
BOGUS1)             |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
BOGUS2)             |
+                       P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT,
BOGUS3))            |
+               p4_config_pack_cccr(P4_CCCR_THRESHOLD(15) |
P4_CCCR_COMPLEMENT          |
+                       P4_CCCR_COMPARE);
+}
+

No new hidden event, just a x86_pmu + a per-arch callbacks.
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