Re: [PATCH v2 2/2] crypto, x86: SSSE3 based SHA1 implementation for x86-64

[Andrew Lutomirski]

On Thu, Aug 11, 2011 at 11:08 AM, Herbert Xu
<herbert@xxxxxxxxxxxxxxxxxxxx> wrote:
> On Thu, Aug 11, 2011 at 10:50:49AM -0400, Andy Lutomirski wrote:
>>
>>> This is pretty similar to the situation with the Intel AES code.
>>> Over there they solved it by using the asynchronous interface and
>>> deferring the processing to a work queue.
>>
>> I have vague plans to clean up extended state handling and make
>> kernel_fpu_begin work efficiently from any context.  (i.e. the first
>> kernel_fpu_begin after a context switch could take up to ~60 ns on Sandy
>> Bridge, but further calls to kernel_fpu_begin would be a single branch.)
>
> This is all well and good but you still need to deal with the
> case of !irq_fpu_usable.

I think I can even get rid of that.  Of course, until that happens,
code still needs to handle !irq_fpu_usable.

(Also, calling these things kernel_fpu_begin() is dangerous.  It's not
actually safe to use floating-point instructions after calling
kernel_fpu_begin.  Integer SIMD instructions are okay, though.  The
issue is that kernel_fpu_begin doesn't initialize MXCSR, and there are
MXCSR values that will cause any floating-point instruction to trap
regardless of its arguments.)

--Andy
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