Re: [PATCH 06/12] perf_events: implement PERF_SAMPLE_BRANCH forIntel X86

[Peter Zijlstra]

On Thu, 2011-10-06 at 16:49 +0200, Stephane Eranian wrote:
> @@ -876,6 +889,13 @@ static void intel_pmu_disable_event(struct perf_event *event)
>                 return;
>         }
>  
> +       /*
> +        * must disable before any actual event
> +        * because any event may be combined with LBR
> +        */
> +       if (intel_pmu_needs_lbr_smpl(event))
> +               intel_pmu_lbr_disable(event);
> +
>         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
>                 intel_pmu_disable_fixed(hwc);
>                 return; 

I don't get that, since until you disable the counter a PMI could happen
(*) you'd need to disable the LBR after you disable the counters.

* doesn't actually happen since we likely have the whole pmu disabled
here, but that's another thing ;-)
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