Re: [PATCH] intel-iommu: Default to non-coherent for domainsunattached to iommus

[David Woodhouse]

On Fri, 2011-11-11 at 17:08 -0800, Chris Wright wrote:
> All the stale PTE issues I've encountered in the past have turned into
> fixed sw bugs (perhaps it's since been fixed?).  Also, I thought with
> Coherency On/Off it's only effecting the use of clflush, not IOTLB or
> Context Entry cache flushing (invalidations).

Yeah, it's supposed to be *just* clflush. Nevertheless, I can imagine it
being screwed up and there actually being a buffer in the chipset too.
We certainly made that mistake with the graphics engine in some cases...

> On a slightly separate, but performance related note...have you ever
> tried using the hw queue?  Currently we only have a sw queue, but the
> submission path for invalidations doesn't really queue (unless I missed
> it).  It seems to pull from the software queue and submit/wait,
> submit/wait...Seems simple enough to submit the whole queue and then
> issue the wait.

I have a feeling we trigger errata if we do that â although if we're
only doing it for an emulated IOMMU that shouldn't be an issue.

-- 
dwmw2

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