Re: [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes

From: Chris Wilson
Date: Wed Mar 28 2012 - 14:41:37 EST

On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz <djkurtz@xxxxxxxxxxxx> wrote:
> The GMBUS controller GMBUS3 register is double-buffered. Take advantage
> of this by writing two 4-byte words before the first wait for HW_RDY.
> This helps keep the GMBUS controller from becoming idle during long writes.
> Signed-off-by: Daniel Kurtz <djkurtz@xxxxxxxxxxxx>

"For byte counts that are greater than four bytes, this register will be
written with subsequent data only after the HW_RDY status bit is set"

Hmm, I had interpretted that as should only be. But if you take into
account that the register is indeed double-buffered, it does make sense
that the hardware itself is only updated after the HW_RDY signal.
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>

Chris Wilson, Intel Open Source Technology Centre
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