Re: [PATCH 2/2] x86/mce: Add instruction recovery signatures tomce-severity table

From: Borislav Petkov
Date: Mon May 14 2012 - 13:23:37 EST

On Mon, May 14, 2012 at 04:28:35PM +0000, Luck, Tony wrote:
> > > I'm trying to figure out a quirk for processors that do generate
> > > EIPV=RIPV=0 signature for IFU errors. There are some case where
> > > we can work around the lack of EIPV.
> >
> > __mcheck_cpu_apply_quirks?
> The quirk is a bit more extensive than just setting some flag in there
> for "if (c->x86 == 6 && c->x86_model == 45)". Sometime EIPV isn't set
> because the regs->ip and regs->cs really aren't valid. So I'll need
> to do something like:
> if (we are on Intel family 6 model 45 AND
> this is a UC=1, PCC=0, AR=1, S=1, ADDRV=1, MCACOD=0x150 error AND
> (virtophys(regs->ip) >> PAGE_SHIFT) == (MC(bank)_ADDR >> PAGE_SHIFT)) {
> /* ok to trust CS & IP */
> m.mcgstatus |= MCG_STATUS_EIPV;
> }

Hmm, maybe add a flag to struct mce or whatever comes handy in that
codepath which says ->on_this_cpu_it_is_ok_to_set_MCG_STATUS_EIPV and
query it in the mce_severity() thing?

Btw, this severities deal could be much more helpful if it were a bunch
of per-vendor, per-bank or whatever function pointers so that you can do
arbitrary filtering there.

> before running through the mce_severity() table lookup.
> x86 doesn't seem to have a "virtophys()" that I can find. Closest is lookup_address(vaddr, level)
> which gets a pte (which is almost all the work).
> Sigh!

What does __pa() do actually?

Oh, that's only for kernel memory, it seems.


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