Re: [PATCH 0/3] PCI: P2P bridge window fixes

[Bjorn Helgaas]

On Mon, Jul 9, 2012 at 9:24 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote:
> On Mon, Jul 9, 2012 at 2:31 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote:
>> Two fixes here:
>>
>> 1) Zero is a legal P2P bridge window base and BAR value and is likely to
>> occur when there is an offset between bus addresses and CPU addresses.
>> Stop disallowing it.
>>
>> 2) The Intel-specific 1K I/O window granularity for P2P bridges was
>> implemented in a way that precluded reassignment of the window after
>> FINAL quirks.  Fix that.
>>
>> And also replace the sparc pci_cfg_fake_ranges() with the functionally
>> equivalent generic version.
>>
>> ---
>>
>> Bjorn Helgaas (3):
>>       PCI: allow P2P bridge windows starting at PCI bus address zero
>>       PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)
>>       sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases()
>>
>>
>>  arch/sparc/kernel/pci.c  |   89 +---------------------------------------------
>>  drivers/pci/probe.c      |   31 +++++++++-------
>>  drivers/pci/quirks.c     |   39 +-------------------
>>  drivers/pci/setup-bus.c  |   11 +++++-
>>  include/linux/pci.h      |    1 +
>>  include/linux/pci_regs.h |    3 +-
>>  6 files changed, 31 insertions(+), 143 deletions(-)
>
> I applied these, as well as Yinghai's patch for 1K support in
> pbus_size_io(), to my "next" branch.  Thanks, Yinghai!

FYI, I just rebased my "next" branch to fix the authorship of
Yinghai's patch.  Only the merge of these four patches (the most
recent merge) is affected.
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