[PATCH 31/34] perf, x86: Add a Haswell precise instructions event

From: Andi Kleen
Date: Thu Oct 18 2012 - 19:24:33 EST

From: Andi Kleen <ak@xxxxxxxxxxxxxxx>

Add a instructions-p event alias that uses the PDIR randomized instruction
retirement event. This is useful to avoid some systematic sampling shadow
problems. Normally PEBS sampling has a systematic shadow. With PDIR
enabled the hardware adds some randomization that statistically avoids
this problem. In this sense, it's more precise over a whole sampling
interval, but an individual sample can be less precise. But since we
sample overall it's a more precise event.

This could be used before using the explicit event code syntax, but it's easier
and more user friendly to use with an "instructions-p" alias. I expect
this will eventually become a common use case.

Right now for Haswell, will add to Ivy Bridge later too.

Signed-off-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
arch/x86/kernel/cpu/perf_event_intel.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 94389a9..a734b6a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2085,6 +2085,7 @@ PMU_EVENT(cycles_t, "cycles-t", "event=0x3c,intx=1");
PMU_EVENT(cycles_ct, "cycles-ct", "event=0x3c,intx=1,intx_cp=1");
PMU_EVENT(insns_t, "instructions-t", "event=0xc0,intx=1");
PMU_EVENT(insns_ct, "instructions-ct","event=0xc0,intx=1,intx_cp=1");
+PMU_EVENT(insns_prec, "instructions-p", "event=0xc0,umask=0x01,precise=2");

#define PMU_EVENT_PTR(x) &attr_ ## x .attr.attr

@@ -2107,6 +2108,7 @@ static struct attribute *hsw_events_attrs[] = {
+ PMU_EVENT_PTR(insns_prec),


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