[PATCH V3 0/5] perf, amd: Enable AMD family 15h northbridge counters
From: Jacob Shin
Date: Mon Nov 26 2012 - 17:49:01 EST
The following patchset enables 4 additional performance counters in
AMD family 15h processors that counts northbridge events -- such as
number of DRAM accesses.
This patchset is based on previous work done by Robert Richter
<rric@xxxxxxxxxx> :
https://lkml.org/lkml/2012/6/19/324
The main differences are:
* The northbridge counters are indexed contiguously right above the
core performance counters.
* MSR address offset calculations are moved to architecture specific
files.
* Interrups are set up to be delivered only to a single core.
V3:
Addressed the following feedback/comments from Robert's review
* https://lkml.org/lkml/2012/11/16/484
* https://lkml.org/lkml/2012/11/26/162
V2:
Separate out Robert's patches, and add properly ordered certificate of
origins.
Jacob Shin (3):
perf, x86: Move MSR address offset calculation to architecture
specific files
perf, amd: Enable northbridge performance counters on AMD family 15h
perf, amd: Use proper naming scheme for AMD bit field definitions
Robert Richter (2):
perf, amd: Rework northbridge event constraints handler
perf, amd: Generalize northbridge constraints code for family 15h
arch/x86/include/asm/cpufeature.h | 2 +
arch/x86/include/asm/msr-index.h | 2 +
arch/x86/include/asm/perf_event.h | 13 +-
arch/x86/kernel/cpu/perf_event.h | 21 +--
arch/x86/kernel/cpu/perf_event_amd.c | 269 ++++++++++++++++++++++++----------
5 files changed, 211 insertions(+), 96 deletions(-)
--
1.7.9.5
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