RE: RE: [PATCH v2 1/2] clk: divider: prepare for minimum divider

[Mohammed, Afzal]

Hi Mike,

On Thu, Jan 24, 2013 at 22:36:30, Mike Turquette wrote:
> Quoting Mohammed, Afzal (2013-01-24 03:29:15)

> > It is a functional constraint: divider has 8 bits and it can have
> > all possible values (0 to 255) and divider value corresponds to
> > value set in the 8 bits. But depending on the modes the minimum
> > value that can be configured (to get display working) varies.
> > Eg. For raster mode (which the driver is presently supporting), it
> > can take a minimum value of 2, while in LIDD (LCD interface display
> > driver) mode it can take a min value of 1.
> > 
> > Here min rate is not a constraint w.r.t divider in LCDC IP, but
> > rather min divider.

> Just so I understand correctly... you are saying that the functional
> constraint is not caused by the clock rate, but instead by the divider
> value?  For the different modes (raster vs LIDD) is the clock rate the
> same, or is the clock rate different?

> What is the clock output rate of the divider in raster mode?  What is
> the clock output rate of the divider in LIDD mode?

Yes, functional constraint in caused by divider value.

clock output rate can defined for both modes as follows,

p_clk (clock output rate) = lcd_clk (input clock rate) / div,

to configure "div", we have r/w 8 bits, so div values can
range from 0-255,

And IP spec says value "0" and "1" should not be written, in
raster mode. Further it says if in LIDD mode it can have values
from 0-255, but effect of writing "0" is same as "1".

Effect of divider value on output rate is in the same way for
both modes as per above expression (except for writing "0" in
LIDD mode).

The driver supports only raster mode.

Regards
Afzal

Note: link to trm has been mentioned in the earlier reply.



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