From 1ed227b4a690da075e6e9068bc16131edbd03c96 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 29 Jan 2013 07:59:07 -0500 Subject: [PATCH] drm/radeon: fix MC blackout on r5xx-r7xx (v2) Force the crtc mem requests on/off immediately rather than waiting for the double buffered updates to kick in. Seems we miss the update in certain conditions. Based on a similar fix for evergreen. v2: take the grph lock when updating the new display base addresses. Reported-by: Shuah Khan Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/r500_reg.h | 1 + drivers/gpu/drm/radeon/rv515.c | 8 ++++++++ 2 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h index ec576aa..5159f0d 100644 --- a/drivers/gpu/drm/radeon/r500_reg.h +++ b/drivers/gpu/drm/radeon/r500_reg.h @@ -358,6 +358,7 @@ #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 +#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8 /* master controls */ #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 2bb6d0e..c736b4a 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -304,7 +304,9 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { radeon_wait_for_vblank(rdev, i); tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); } /* wait for the next frame */ frame_count = radeon_get_vblank_counter(rdev, i); @@ -345,6 +347,8 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) /* update crtc base addresses */ for (i = 0; i < rdev->num_crtc; i++) { + WREG32_P(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], + AVIVO_D1GRPH_UPDATE_LOCK, ~AVIVO_D1GRPH_UPDATE_LOCK); if (rdev->family >= CHIP_RV770) { if (i == 1) { WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, @@ -362,6 +366,8 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) (u32)rdev->mc.vram_start); WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], (u32)rdev->mc.vram_start); + WREG32_P(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], + 0, ~AVIVO_D1GRPH_UPDATE_LOCK); } WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); @@ -384,7 +390,9 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) if (save->crtc_enabled[i]) { tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); /* wait for the next frame */ frame_count = radeon_get_vblank_counter(rdev, i); for (j = 0; j < rdev->usec_timeout; j++) { -- 1.7.7.5