Re: [PATCH] clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}

[Olof Johansson]

On Tue, Apr 23, 2013 at 12:01:51PM +0530, Tushar Behera wrote:
> commit 688f7d8c9fef ("clk: exynos5250: Fix divider values for
> sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3}
> to fix the wrong clock value. Though this fixed issue with Arndale,
> it created regressions for other boards like Snow.
> 
> On Exynos5250, sclk_mmc<n> is generated like below (as per the clock
> names in drivers/clk/samsung/clk-exynos5250.c)
> 
> mout_group1_p ==> mout_mmc<n> ==>
> 		div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n>
> 
> Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence
> div_mmc_pre<n> was not getting referred in kernel code and depending
> on its value set during preboot, sclk_mmc<n> value was different for
> various boards.
> 
> Setting the correct clock generation path should fix the issues
> reported in above referenced commit. The changes committed during the
> earlier patch has also been reverted here.
> 
> Signed-off-by: Tushar Behera <tushar.behera@xxxxxxxxxx>
> CC: Doug Anderson <dianders@xxxxxxxxxxxx>
> ---
> Doug,
> 
> Would you please test whether this patch works for Snow?

Applied to next/drivers in arm-soc.git.


-Olof

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