Subject: [PATCH 2/2] PCI: Skip IORESOURCE_IO size and allocation for root bus without ioport range BenH reported that there is some assign unassigned resource problem in powerpc. It turns out after | commit 0c5be0cb0edfe3b5c4b62eac68aa2aa15ec681af | Date: Thu Feb 23 19:23:29 2012 -0800 | | PCI: Retry on IORESOURCE_IO type allocations even the root bus does not have io port range, it will keep retrying to realloc with mmio. Current retry logic is : try with must+optional at first, and if it fails will try must then try to extend must with optional. That will fail as mmio-non-pref and mmio-pref for bridge will be next to each other. So we have no chance to extend mmio-non-pref. We should not fall into retry in this case, as root bus does not io port range. We check if the root bus has ioport range, and set bus_res_type_mask, and pass it to __bus_size_bridges and skip io port resources. For the retry failing, we could allocate mmio-non-pref bottom-up and mmio-pref will be top-down, but that could not be material for v3.10. -v2: remove wrong __init with pci_bus_res_type_mask() don't check bridge size/flags, and clear bus io resources. Reported-by: Benjamin Herrenschmidt Signed-off-by: Yinghai Lu --- drivers/pci/setup-bus.c | 81 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 64 insertions(+), 17 deletions(-) Index: linux-2.6/drivers/pci/setup-bus.c =================================================================== --- linux-2.6.orig/drivers/pci/setup-bus.c +++ linux-2.6/drivers/pci/setup-bus.c @@ -586,7 +586,8 @@ void pci_setup_bridge(struct pci_bus *bu /* Check whether the bridge supports optional I/O and prefetchable memory ranges. If not, the respective base/limit registers must be read-only and read as 0. */ -static void pci_bridge_check_ranges(struct pci_bus *bus) +static void pci_bridge_check_ranges(struct pci_bus *bus, + unsigned long res_type_mask) { u16 io; u32 pmem; @@ -596,14 +597,17 @@ static void pci_bridge_check_ranges(stru b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; b_res[1].flags |= IORESOURCE_MEM; - pci_read_config_word(bridge, PCI_IO_BASE, &io); - if (!io) { - pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); + if (res_type_mask & IORESOURCE_IO) { pci_read_config_word(bridge, PCI_IO_BASE, &io); - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); - } - if (io) - b_res[0].flags |= IORESOURCE_IO; + if (!io) { + pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); + pci_read_config_word(bridge, PCI_IO_BASE, &io); + pci_write_config_word(bridge, PCI_IO_BASE, 0x0); + } + if (io) + b_res[0].flags |= IORESOURCE_IO; + } + /* DECchip 21050 pass 2 errata: the bridge may miss an address disconnect boundary by one PCI data phase. Workaround: do not use prefetching on this device. */ @@ -812,6 +816,24 @@ static void pbus_size_io(struct pci_bus } } +static void pbus_clear_io(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + int i; + + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + struct resource *r = &dev->resource[i]; + + if (r->parent || !(r->flags & IORESOURCE_IO)) + continue; + + reset_resource(r); + } + } +} + static inline resource_size_t calculate_mem_align(resource_size_t *aligns, int max_order) { @@ -1045,7 +1067,8 @@ handle_done: } static void __ref __pci_bus_size_bridges(struct pci_bus *bus, - struct list_head *realloc_head) + struct list_head *realloc_head, + unsigned long res_type_mask) { struct pci_dev *dev; unsigned long mask, prefmask; @@ -1063,7 +1086,7 @@ static void __ref __pci_bus_size_bridges case PCI_CLASS_BRIDGE_PCI: default: - __pci_bus_size_bridges(b, realloc_head); + __pci_bus_size_bridges(b, realloc_head, res_type_mask); break; } } @@ -1078,7 +1101,7 @@ static void __ref __pci_bus_size_bridges break; case PCI_CLASS_BRIDGE_PCI: - pci_bridge_check_ranges(bus); + pci_bridge_check_ranges(bus, res_type_mask); if (bus->self->is_hotplug_bridge) { additional_io_size = pci_hotplug_io_size; additional_mem_size = pci_hotplug_mem_size; @@ -1087,8 +1110,11 @@ static void __ref __pci_bus_size_bridges * Follow thru */ default: - pbus_size_io(bus, realloc_head ? 0 : additional_io_size, - additional_io_size, realloc_head); + if (res_type_mask & IORESOURCE_IO) + pbus_size_io(bus, realloc_head ? 0 : additional_io_size, + additional_io_size, realloc_head); + else + pbus_clear_io(bus); /* If the bridge supports prefetchable range, size it separately. If it doesn't, or its prefetchable window has already been allocated by arch code, try @@ -1111,7 +1137,10 @@ static void __ref __pci_bus_size_bridges void __ref pci_bus_size_bridges(struct pci_bus *bus) { - __pci_bus_size_bridges(bus, NULL); + unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH; + + __pci_bus_size_bridges(bus, NULL, type_mask); } EXPORT_SYMBOL(pci_bus_size_bridges); @@ -1376,6 +1405,21 @@ static enum enable_type __init pci_reall return enable_local; } +static unsigned long pci_bus_res_type_mask(struct pci_bus *bus) +{ + int i; + struct resource *r; + unsigned long mask = 0; + unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH; + + pci_bus_for_each_resource(bus, r, i) + if (r) + mask |= r->flags & type_mask; + + return mask; +} + /* * first try will not touch pci bridge res * second and later try will clear small leaf bridge res @@ -1395,6 +1439,7 @@ pci_assign_unassigned_root_bus_resources IORESOURCE_PREFETCH; int pci_try_num = 1; enum enable_type enable_local; + unsigned long bus_res_type_mask = pci_bus_res_type_mask(bus); /* don't realloc if asked to do so */ enable_local = pci_realloc_detect(bus, pci_realloc_enable); @@ -1416,7 +1461,7 @@ again: add_list = &realloc_head; /* Depth first, calculate sizes and alignments of all subordinate buses. */ - __pci_bus_size_bridges(bus, add_list); + __pci_bus_size_bridges(bus, add_list, bus_res_type_mask); /* Depth last, allocate resources and update the hardware. */ __pci_bus_assign_resources(bus, add_list, &fail_head); @@ -1496,9 +1541,10 @@ void pci_assign_unassigned_bridge_resour int retval; unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH; + unsigned long bus_res_type_mask = pci_bus_res_type_mask(bridge->bus); again: - __pci_bus_size_bridges(parent, &add_list); + __pci_bus_size_bridges(parent, &add_list, bus_res_type_mask); __pci_bridge_assign_resources(bridge, &add_list, &fail_head); BUG_ON(!list_empty(&add_list)); tried_times++; @@ -1554,6 +1600,7 @@ void pci_assign_unassigned_bus_resources struct pci_dev *dev; LIST_HEAD(add_list); /* list of resources that want additional resources */ + unsigned long bus_res_type_mask = pci_bus_res_type_mask(bus); down_read(&pci_bus_sem); list_for_each_entry(dev, &bus->devices, bus_list) @@ -1561,7 +1608,7 @@ void pci_assign_unassigned_bus_resources dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) if (dev->subordinate) __pci_bus_size_bridges(dev->subordinate, - &add_list); + &add_list, bus_res_type_mask); up_read(&pci_bus_sem); __pci_bus_assign_resources(bus, &add_list, NULL); BUG_ON(!list_empty(&add_list));