Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
From: Mike Qiu
Date: Wed May 22 2013 - 02:16:36 EST
ä 2013/5/22 8:15, Benjamin Herrenschmidt åé:
On Tue, 2013-05-21 at 16:45 +0200, Alexander Gordeev wrote:
On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote:
The test results is shown by 'cat /proc/interrups':
CPU0 CPU1 CPU2 CPU3
16: 240458 261601 226310 200425 XICS Level IPI
17: 0 0 0 0 XICS Level RAS_EPOW
18: 10 0 3 2 XICS Level hvc_console
19: 122182 28481 28527 28864 XICS Level ibmvscsi
20: 506 7388226 108 118 XICS Level eth0
21: 6 5 5 5 XICS Level host1-0
22: 817 814 816 813 XICS Level host1-1
Hi Mike,
I am curious if pSeries firmware allows changing affinity masks independently
for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21
and IRQ22 to different CPUs?
Yes. Each interrupt has its own affinity, whether it's an MSI or not,
the affinity is not driven by the address.
Cheers,
Ben.
Hi Ben,
May this patch be accepted? if so I will send out the 3.9 version.
As Michael Ellerman says, he want to see the performance data,
but this depends on the driver.
It is something like MSI, and the driver can use more than 1 MSI.
That is to say, the driver has more interrupt resource to use,
but whether the driver is full use of the resource, is out of
this patch's control.
I test this patch use ipr driver, which add multiple MSI
support by others. and it can work.
Thanks
Mike
Thanks!
LOC: 398077 316725 231882 203049 Local timer interrupts
SPU: 1659 919 961 903 Spurious interrupts
CNT: 0 0 0 0 Performance
monitoring interrupts
MCE: 0 0 0 0 Machine check exceptions
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