On Tue, Jun 04, 2013 at 08:15:45AM +0200, Michal Simek wrote:On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:On 08:58 Tue 14 May , Hein Tibosch wrote:On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:so no it will not workOn May 14, 2013, at 12:05 AM, Nicolas Ferre <nicolas.ferre@xxxxxxxxx> wrote:
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)can we detect it via the IP?
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <hein_tibosch@xxxxxxxx>
Signed-off-by: Nicolas Ferre <nicolas.ferre@xxxxxxxxx>
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
as the gem on sama5 is 00020119
so version 0x119 too
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@xxxxxxxxxxxx>
Was this added to any queue or branch?
I would like to enable macb for zynq and not sure if "cdns,zynq-7000-gem"
compatible string goes to mainline.
This is already in next, but you can use the default compatible as the
DCR1 is used instead of DT binding.