Re: [PATCH v5] i2c: omap: correct usage of the interrupt enableregister
From: Wolfram Sang
Date: Wed Jun 19 2013 - 06:03:14 EST
On Mon, Jun 03, 2013 at 10:37:20AM +0300, Oleksandr Dmytryshyn wrote:
> We've been lucky not to have any interrupts fire during the suspend
> path, otherwise we would have unpredictable behaviour in the kernel.
> Based on the logic of the kernel code interrupts from i2c should be
> prohibited during suspend. Kernel writes 0 to the I2C_IE register in
> the omap_i2c_runtime_suspend() function. In the other side kernel
> writes saved interrupt flags to the I2C_IE register in
> omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
> during suspend.
> This works for chips with version1 registers scheme. Interrupts are
> disabled during suspend. For chips with version2 scheme registers
> writting 0 to the I2C_IE register does nothing (because now the
> I2C_IRQENABLE_SET register is located at this address). This register
> is used to enable interrupts. For disabling interrupts
> I2C_IRQENABLE_CLR register should be used.
> Because the registers I2C_IRQENABLE_SET and I2C_IE have the same
> addresses, the interrupt enabling procedure is unchanged.
> I've checked that interrupts in the i2c controller are still enabled
> after writting 0 to the I2C_IRQENABLE_SET register. With this patch
> interrupts are disabled in the omap_i2c_runtime_suspend() function.
> Patch is based on:
> tag: v3.10-rc2
Last paragraph should be below "---".
> Verified on OMAP4430.
> Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@xxxxxx>
Applied to for-next, thanks!
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