Re: [PATCH V9 1/4] pci: Add PCIe driver for Samsung Exynos
From: Sachin Kamat
Date: Fri Jun 21 2013 - 00:11:18 EST
Some small corrections inline.
On 21 June 2013 08:51, Jingoo Han <jg1.han@xxxxxxxxxxx> wrote:
> Exynos5440 has a PCIe controller which can be used as Root Complex.
> This driver supports a PCIe controller as Root Complex mode.
> Signed-off-by: Surendranath Gurivireddy Balla <suren.reddy@xxxxxxxxxxx>
> Signed-off-by: Siva Reddy Kallam <siva.kallam@xxxxxxxxxxx>
> Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
> Acked-by: Arnd Bergmann <arnd@xxxxxxxx>
> .../devicetree/bindings/pci/designware-pcie.txt | 73 ++
> drivers/pci/host/Kconfig | 9 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pci-designware.c | 1057 ++++++++++++++++++++
> 4 files changed, 1140 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt
> create mode 100644 drivers/pci/host/pci-designware.c
> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> new file mode 100644
> index 0000000..e4681e6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> @@ -0,0 +1,73 @@
> +* Synopsis Designware PCIe interface
> +Required properties:
> +-compatible: should contain "snps,dw-pcie" to identify the
> + core, plus an identifier for the specific instance, such
> + as "samsung,exynos5440-pcie".
> +-reg: base addresses and lengths of the pcie conteroller,
> + the phy controller, additional register for the phy controller.
> +- interrupts: interrupt values for level interrupt,
> + pulse interrupt, special interrupt.
> +- clocks: from common clock binding: handle to pci clock.
> +- clock-names: from common clock binding: Shall be "pcie", "pcie_bus".
s/Shall be .../should be "pcie" and "pcie_bus".
> +MODULE_AUTHOR("Jingoo Han <jg1.han@xxxxxxxxxxx>");
> +MODULE_DESCRIPTION("Samsung PCIe host controller driver");
I think this should be "GPL v2" (with a space between GPL and v2).
With warm regards,
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