Re: [LINUX PATCH RFC v2] trafgen: xilinx: add axi traffic generatordriver

From: Michal Simek
Date: Fri Jul 26 2013 - 08:22:50 EST

Hi Greg and Arnd,

On 07/20/2013 05:01 PM, Srikanth Thokala wrote:
> This is the driver for AXI Traffic Generator IP. The AXI
> Traffic Generator IP is a core that stresses the AXI4
> interconnect and other AXI4 peripherals in the system.
> It generates a wide variety of AXI4 transactions based on
> the core programming.
> Architecture of the core is broadly separated into a master
> and slave block, each of which contains the write block and
> read block. Other support functions are provided by the
> control registers and three internal RAMs - Master RAM,
> Command RAM, Parameter RAM. The initialisation sequence
> includes programming Command RAM with commands, data into
> Master RAM (optional Parameter RAM programming) and then
> enable master logic using control register interface.
> This sequence generates traffic to cores connected in the
> h/w design.
> The driver for this IP is designed to be a module with
> sysfs interface. All the control registers and internal
> RAMs can be accessed through sysfs interface.
> Signed-off-by: Srikanth Thokala <sthokal@xxxxxxxxxx>
> Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
> ---
> v2: Documented sysfs functions

Do you have any concern about this patch?


Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu -
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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