Re: [PATCH v2 2/2] gpio MIPS/OCTEON: Add a driver for OCTEON'son-chip GPIO pins.

[Linus Walleij]

On Mon, Jul 29, 2013 at 11:29 PM, David Daney <ddaney.cavm@xxxxxxxxx> wrote:

> From: David Daney <david.daney@xxxxxxxxxx>
>
> The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
> GPIO pins, this driver handles them all.  Configuring the pins as
> interrupt sources is handled elsewhere (OCTEON's irq handling code).
>
> Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
> ---
>
> Device tree binding defintions already exist for this device in
> Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt

I like this.
Reviewed-by: Linus Walleij <linus.walleij@xxxxxxxxxx>

I guess you will merge both patches through the MIPS arch
tree?

Yours,
Linus Walleij
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