Re: perf events ring buffer memory barrier on powerpc
From: Peter Zijlstra
Date: Fri Nov 01 2013 - 12:18:37 EST
On Wed, Oct 30, 2013 at 11:40:15PM -0700, Paul E. McKenney wrote:
> The dependency you are talking about is via the "if" statement?
> Even C/C++11 is not required to respect control dependencies.
> This one is a bit annoying. The x86 TSO means that you really only
> need barrier(), ARM (recent ARM, anyway) and Power could use a weaker
> barrier, and so on -- but smp_mb() emits a full barrier.
> Perhaps a new smp_tmb() for TSO semantics, where reads are ordered
> before reads, writes before writes, and reads before writes, but not
> writes before reads? Another approach would be to define a per-arch
> barrier for this particular case.
Supposing a sane language where we can rely on control flow; would that
change the story?
I'm afraid I'm now terminally confused between actual proper memory
model issues and fucked compilers.
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