Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
From: Vivek Gautam
Date: Tue Nov 05 2013 - 02:12:15 EST
On Tue, Nov 5, 2013 at 11:06 AM, Vivek Gautam <gautamvivek1987@xxxxxxxxx> wrote:
> Hi Tomasz,
Sorry my mail client had some problem, so forwarding this again.
> On Nov 4, 2013 5:59 PM, "Tomasz Figa" <t.figa@xxxxxxxxxxx> wrote:
>> Hi Kishon,
>> On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote:
>> > Hi Vivek,
>> > On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote:
>> > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
>> > > The new driver uses the generic PHY framework and will interact
>> > > with DWC3 controller present on Exynos5 series of SoCs.
>> > In Exynos, you have a single IP that supports both USB3 and USB2 PHY
>> > right? I think that needs to be mentioned here.
>> Nope. There are two separate, different IPs.
> AFAICS the dwc3 controller (aka usb 3.0 drd controller, as mentioned in
> exynos5 UM) uses a combo of usb 2 (utmi+) and usb 3 (pipe 3) phy (with base
> address starting 0x12100000), thereby giving the driver only freedom to
> control them as one. The entire set of registers with base 0x12100000 for
> exynos5250 and later 0x12500000 for exynos5420 are being programmed by this
> driver. That's the reason i structured the driver this way, and thereby it
> makes the dwc3 controller to just use only single phy.
> Please correct me if i am wrong.
>> > Do you have separate registers that should be used for
>> > initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If
>> > so, then you should model this driver as a single driver that supports
>> > two PHYs similar to what Sylwester has done before?
>> Sylwester's MIPI PHY uses such model because it has a single register
>> that controls both PHYs.
>> Best regards,
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