Re: [PATCH v3 3/5] MCS Lock: Barrier corrections

From: Michel Lespinasse
Date: Thu Nov 07 2013 - 07:50:28 EST

On Thu, Nov 7, 2013 at 4:06 AM, Linus Torvalds
<torvalds@xxxxxxxxxxxxxxxxxxxx> wrote:
> On Nov 7, 2013 6:55 PM, "Michel Lespinasse" <walken@xxxxxxxxxx> wrote:
>> Rather than writing arch-specific locking code, would you agree to
>> introduce acquire and release memory operations ?
> Yes, that's probably the right thing to do. What ops do we need? Store with
> release, cmpxchg and load with acquire? Anything else?

Depends on what lock types we want to implement on top; for MCS we would need:
- xchg acquire (common case) and load acquire (for spinning on our
locker's wait word)
- cmpxchg release (when there is no next locker) and store release
(when writing to the next locker's wait word)

One downside of the proposal is that using a load acquire for spinning
puts the memory barrier within the spin loop. So this model is very
intuitive and does not add unnecessary barriers on x86, but it my
place the barriers in a suboptimal place for architectures that need

Michel "Walken" Lespinasse
A program is never fully debugged until the last user dies.
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