Re: [PATCH v7 3/4] perf,x86: add Intel RAPL PMU support

[Vince Weaver]

On Thu, 28 Nov 2013, Stephane Eranian wrote:

> On Thu, Nov 28, 2013 at 1:26 PM, Ingo Molnar <mingo@xxxxxxxxxx> wrote:
> >
> > * Vince Weaver <vince@xxxxxxxxxx> wrote:
> >
> >> On Wed, 27 Nov 2013, Stephane Eranian wrote:
> >>
> >> > On Wed, Nov 27, 2013 at 7:35 PM, Vince Weaver <vince@xxxxxxxxxx> wrote:
> >>
> >> > > So I notice PP1 (which is the GPU power on non-server chips)
> >> > > is not supported.
> >> > >
> >> > > Is that just for simplicity?
> >> > >
> >> > Does it work on specific models only? I bet so. How to detect those?
> >>
> >> In general it is on the machines that don't support the DRAM measurements
> >> (so the non-EP machines) but I don't know if there's a nice list anywhere.
> >>
> >> Intel manuals say:
> >>    For a client platform, PP1 domain refers to the power plane of a
> >>    specific device in the uncore. For server platforms, PP1 domain is not
> >>    supported,
> >>
> >> usually PP1 I think maps to the embedded GPU.
> >
> > It would indeed be nice to expose PP1 too via the same facility -
> > Haswell and later spends some 40% of the CPU die on the integrated GPU
> > and people end up using it.
> >
> My worry is to determine if the GPU is actually enabled or even present.
> Using the x86_model may not be enough for that.

In my experience if the device is not there you just get 0s as results
from RAPL (I've also seen this on some Sandybridge-EP machines we have 
that for whatever reason don't support the DRAM RAPL results).

So in theory it would be harmless to export the values even if not 
supported.  What is the worst failure mode?  That somehow a recent CPU 
doesn't support the MSR and we get a GPF when trying to access it?

Vince
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